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John Popelish John Popelish is offline
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Default SMT layout for multi capacitor bypass

Joerg wrote:
John Popelish wrote:

Joerg wrote:


Yep, by having the vias to the ground plane in the pads. But be
prepared for some eggs and tomatoes flying,



Not familiar with that technical expression.


A via inside the footprint of a part is often frowned upon but it's been
done. It can mess with the thermal profile of the solder process.

(snip)

I was referring to "eggs and tomatoes flying". :-)
I have no vias inside the pads in my graphic. The black
lines are the part (min and max size) and pads. the red
lines are the traces and vias.

Here is a version with wider ground traces and the vias
moved right up to the pads.

Attached Thumbnails
SMT layout for multi capacitor bypass-4x0201bypass2-gif