Why does two channels of ADC give different outputs?
"Frank" wrote in message
...
I was aware of this, however now I am asynchronously sampling at 400MHz,
thus
I am expecting each I/Q sample to be stable and correct for at least
22.5ns
assuming
the LA has miscaptured for one 2.5ns cycle.
Are you saying that within one ENC cycle, the data is not stable around the
falling clock edge?
Meindert
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