Frank wrote:
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218).
When I connect I channel from DAC to I & Q channel of ADC, I am seeing
vastly
different digital outputs on ADC (sampling three pins on oscilloscope). What
might
be the cause?

Analog offset and gain difference is most likely. Nonlinearity is
possible. Could a hold capacitor be defective?

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218).
When I connect I channel from DAC to I & Q channel of ADC, I am seeing
vastly
different digital outputs on ADC (sampling three pins on oscilloscope). What
might
be the cause?

"Jerry Avins" wrote in message
...
Frank wrote:
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog
AD9218).
When I connect I channel from DAC to I & Q channel of ADC, I am seeing
vastly
different digital outputs on ADC (sampling three pins on oscilloscope).
What
might
be the cause?

Analog offset and gain difference is most likely. Nonlinearity is
possible. Could a hold capacitor be defective?

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

OMG! There are 3 ADC boards in my lab, all of them had been badly tampered
and the one I am
using is the least tampered piece. Maybe I am really doomed. :-(

"Frank" wrote in message
...
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218).
When I connect I channel from DAC to I & Q channel of ADC, I am seeing
vastly
different digital outputs on ADC (sampling three pins on oscilloscope).
What
might
be the cause?




When using logic analyzer to sample ADC outputs, i am getting strange
outputs.

Right channel,
bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies
during active, while sticking to
1 during idle mode.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).

I double checked my settings, but found nothing wrong. How can I proceed
now?

"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
When using logic analyzer to sample ADC outputs, i am getting strange
outputs.

Right channel,
bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies
during active, while sticking to
1 during idle mode.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle
mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave
in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).

Do you use any bus control signal (RD in combination with CE for the ADC
for
example) to trigger the logic analyser? If not, you are just measuring
all
bus activity, not just the output from the ADC.

Meindert



In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us. On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

"Frank" wrote in message
...
In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us.
On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

And I am not. this PHY_EN signal, what does it drive on the processor?
I can imagine that it just signals the processor data is available and that
consequently, the processor issues bus cycles (set an address or CE,
activate RD, read data, deactivate Rd and CE) to read the data. This means
that data on the bus during this 30us is not data from the ADC all the time.
Only when the ADC is read during the bus read cycle, valid ADC data is
readable on the bus.

Meindert

"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us.
On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is
high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

And I am not. this PHY_EN signal, what does it drive on the processor?
I can imagine that it just signals the processor data is available and
that
consequently, the processor issues bus cycles (set an address or CE,
activate RD, read data, deactivate Rd and CE) to read the data. This means
that data on the bus during this 30us is not data from the ADC all the
time.
Only when the ADC is read during the bus read cycle, valid ADC data is
readable on the bus.

Meindert



Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal, it's as
plain as ADC outputs are hold stable and change every 25ns.

After all is done, I think I had better flag a "faulty ADC board" message to
the up layer. since even when I disconnect ADC input, many of the pins
mentioned
below still to high level, sampled by a logic analyzer's 400MHz clock.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).

"Frank" wrote in message
...
Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal, it's
as
plain as ADC outputs are hold stable and change every 25ns.

That is correct. The rising edge of ENCa and b (clock) sample the signal and
on the falling edge, a valid word can be read from the databus. So your
analyzer should trigger on the falling edge of the ENC signal


Meindert

"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal,
it's
as
plain as ADC outputs are hold stable and change every 25ns.

That is correct. The rising edge of ENCa and b (clock) sample the signal
and
on the falling edge, a valid word can be read from the databus. So your
analyzer should trigger on the falling edge of the ENC signal


Meindert



I was aware of this, however now I am asynchronously sampling at 400MHz,
thus
I am expecting each I/Q sample to be stable and correct for at least 22.5ns
assuming
the LA has miscaptured for one 2.5ns cycle.

"Frank" wrote in message
...
I was aware of this, however now I am asynchronously sampling at 400MHz,
thus
I am expecting each I/Q sample to be stable and correct for at least
22.5ns
assuming
the LA has miscaptured for one 2.5ns cycle.

Are you saying that within one ENC cycle, the data is not stable around the
falling clock edge?

Meindert

"Frank" wrote in message
...

"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for
10us.
On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is
high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

And I am not. this PHY_EN signal, what does it drive on the processor?
I can imagine that it just signals the processor data is available and
that
consequently, the processor issues bus cycles (set an address or CE,
activate RD, read data, deactivate Rd and CE) to read the data. This
means
that data on the bus during this 30us is not data from the ADC all the
time.
Only when the ADC is read during the bus read cycle, valid ADC data is
readable on the bus.

Meindert



Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal, it's
as
plain as ADC outputs are hold stable and change every 25ns.

After all is done, I think I had better flag a "faulty ADC board" message
to
the up layer. since even when I disconnect ADC input, many of the pins
mentioned
below still to high level, sampled by a logic analyzer's 400MHz clock.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle
mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).




Sigh! What should I say!!! After working a number of times, I realized that
the
god damned LA strobes are broken, and managed to sort out the broken ones
with an everchanging pin. With this discovery, I think I will get on much
easier.