"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal,
it's
as
plain as ADC outputs are hold stable and change every 25ns.

That is correct. The rising edge of ENCa and b (clock) sample the signal
and
on the falling edge, a valid word can be read from the databus. So your
analyzer should trigger on the falling edge of the ENC signal


Meindert



I was aware of this, however now I am asynchronously sampling at 400MHz,
thus
I am expecting each I/Q sample to be stable and correct for at least 22.5ns
assuming
the LA has miscaptured for one 2.5ns cycle.