"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us.
On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is
high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

And I am not. this PHY_EN signal, what does it drive on the processor?
I can imagine that it just signals the processor data is available and
that
consequently, the processor issues bus cycles (set an address or CE,
activate RD, read data, deactivate Rd and CE) to read the data. This means
that data on the bus during this 30us is not data from the ADC all the
time.
Only when the ADC is read during the bus read cycle, valid ADC data is
readable on the bus.

Meindert



Ah! I understand what you mean now. PHY_EN is a stable signal, while my
clock
period is 25ns, in each frame, digital side is sending some 1200 I/Q
samples,
one pair of samples each cycle and unchanged throughout the clock cycle.

From the datasheet of ADC, I don't see there is any Rd or CD signal, it's as
plain as ADC outputs are hold stable and change every 25ns.

After all is done, I think I had better flag a "faulty ADC board" message to
the up layer. since even when I disconnect ADC input, many of the pins
mentioned
below still to high level, sampled by a logic analyzer's 400MHz clock.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).