"Frank" wrote in message
...
In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us.
On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is high,
thus I can capture
20 repetitions. I am sure the data capture is correct.

And I am not. this PHY_EN signal, what does it drive on the processor?
I can imagine that it just signals the processor data is available and that
consequently, the processor issues bus cycles (set an address or CE,
activate RD, read data, deactivate Rd and CE) to read the data. This means
that data on the bus during this 30us is not data from the ADC all the time.
Only when the ADC is read during the bus read cycle, valid ADC data is
readable on the bus.

Meindert