"Meindert Sprang" wrote in message
...
"Frank" wrote in message
...
When using logic analyzer to sample ADC outputs, i am getting strange
outputs.

Right channel,
bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies
during active, while sticking to
1 during idle mode.

Left channel,
bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle
mode,
bit 8,6,3,2 switches during
active, stick to 0 during idle (I expect 9:2 of both channel to behave
in
this manner), bit 1:0 are
switching during idle and active (noise during idle mode).

Do you use any bus control signal (RD in combination with CE for the ADC
for
example) to trigger the logic analyser? If not, you are just measuring
all
bus activity, not just the output from the ADC.

Meindert



In my digital side, I have a PHY_EN pin which is high when the digital
circuit repetitively sends
out same data, and the digital circuits work for 30us and idle for 10us. On
logic analyzer, I set
the LA to start filling in the internal memory (256K) once PHY_EN is high,
thus I can capture
20 repetitions. I am sure the data capture is correct.