I have /CE (clock enable) tied to ground, /PL (parallel load) and CLK
are hooked up to individual parallel port lines. It appears as though
the chip doesn't want to perform the parallel load and I've measured
the output (Q7) voltage to be around 2.7V, which, IIRC, is invalid for
CMOS.
How did you measure it? With it in the circuit or have it disconnected
from the next stage. Remember that the load in your next stage
may lower the voltage drop (Did you send to signal to drive many other
chips?).


It doesn't seem to change with clock pulses which is strange.

Could it be that the chip is bad?


Don't know. It seems that you may have a bad chip. Is this your own design
or a chip from a product you have bought?

Or, am I doing the parallel load
wrong? Here's the C code I'm using:

Please post a rather complete schematic so people will see where the
problem is. Thank you.