"Monty Hall" bravely wrote to "All" (27 Dec 04 14:25:15)
--- on the heady topic of "Op-Amp Design - Stage 2 Current to Voltage"

MH Reply-To: "Monty Hall"
MH Xref: aeinews sci.electronics.repair:4845

MH I'm reading Tom Frederickson's "Intuitive IC Op Amps" - in particular
MH pg 15 concerning the op-amp schematic, and am not sure how the second
MH stage of the op amp works. This stage that takes the single ended
MH current and converts it a voltage before it's off to the output stage.

MH The current input goes to the base of a transistor whose emitter is
MH connected directly to ground and the freq compensating capacitor is
MH placed across the collector and base. How does this configuration work
MH - especially if the base input current is negative? Current is sourced
MH from cap?

MH Horowitz and Hill's 741 schematic has a 300 ohm resistor on the base
MH input. Is this where the current to voltage conversion takes place and
MH was omitted by Frederickson? In either case, still not sure where
MH current comes from when current mirror sinks current in stage 1.

MH If the sinking current mirror pulls from the cap, I would expect the
MH mirror, when sourcing current, to load the cap by symmetry. But in a
MH sourcing configuation, the transistor is now forward biased. If
MH current is being sunk
MH @ constant rate, wouldn't the magnitude of the voltage across the cap
MH ramp wrt time? I expected the output voltage to be proportional to
MH input differential voltage and not ramp in an open loop config.

MH Can somebody explain how current is converted to voltage in stage 2 of
MH an op-amp?

MH Totally unrelated, but what does it mean when a NPN transistor has two
MH or more emitters in a schematic?

MH Thanks,


Monty, current is converted to a voltage by flowing through a
resistor. It is that simple as you may have noticed. However the
compensation cap is a dynamic element which must be dealt with as a
small signal AC network and not as a large signal static charging
element. I think this is why you are confused.

To approach the problem from the small signal viewpoint the input
resistance or impedance of the transistor stage must be measured or
approximated (educated guess). In the common emitter transistor, the
base impedance is equal to about Vt/Ib where Ib is the DC base current
and Vt is a constant (but varies with temp) ranging from about 20mV to
40mV (depending on construction), often a 25mV approximation is used.
The effective capacitance across the base impedance is multiplied by
the transistor voltage gain (Miller Multiplication). As an example for
a voltage gain of 100 a 200pF cap reflects as a 20nF cap across the
base impedance. This results in a lp pole to limit the phase shift to
a predictable value for the frequency compensation. If the cap wasn't
used the phase shifts of all the stray caps would add up to make the
amp unstable at some frequency and with a lot of gain. A bad thing.

About multiple emitters, this is a feature of integrated circuits
where the transistor structure divides the collector current into more
than one emitter. This is often done to get very close matching for
temperature compensation or to get a very precise current division.
Sometimes it is simply for isolation between supplied circuits when
used as a reference emitter follower to bias various stages.

Good luck in your studies!

A*s*i*m*o*v

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