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Tauno Voipio Tauno Voipio is offline
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Default Why was the circuit designed to use a Callins in C7?

On 12.12.20 22.14, Don wrote:
In sci.electronics.design Tauno Voipio wrote:
On 12.12.20 19.34, wrote:


snip

Was it designed that way?

That circuit was barely designed at all. What's it supposed to do?



Agreed.

There is a voltage-controlled UJT sawtooth generator, with
outputs sent to three places:

- direct output,

- a differential pair-rectifier to cut it at the
middle for a (maybe) symmetric triangle,

- a Schmitt-trigger to create a variable width pulse

There is plenty of opportunity for improvement even when
using the block diagram (and forgetting the UJT).


You seem to know what you're talking about.

Although its ramp and triangle outputs are now restored, the Schmitt
trigger's still a work in progress. It's (manually transcribed from a
PDF and as typo-free as possible) Design Analysis is shown below. The
last paragraph in the analysis leads me to believe the Callins capacitor
was plausibly used by design.

DESIGN ANALYSIS

The central feature of the 2720-2A VCO is the self-zeroing, summing
voltage to current converter comprising of IC-1, Q1 and associated
components. Unlike the more conventional inverting summer, the feed
back voltage does not come directly from the output of the amplifier
but rather from the emitter of the current source transistor Q1. In
operation positive voltages applied to one or more of the summing
resistors (R1 - R3) force the output of the amplifier to go to
whatever negative voltage is necessary to make the same voltage
appear at both the inverting and non-inverting inputs of the op amp.
Feedback circuits are always a balancing act and the balanced point in
any linear operational amplifier circuit is reached when the two inputs
are at equal voltages. Since in this case the non-inverting input is
grounded (0v.) the inverting input must also go to zero volts.

Since the base emitter junction of Q1 is inside the feedback loop of
the summing amplifier, both the natural non-linearities and constant
voltage drop of the junction are eliminated from the response of the
current source. Both sets of resistors that serve as emitter resistances
for the current source (Range trimmer R7 in series with R6 both
paralleled by R4) terminate at ground and a virtual ground so that for
zero control volts input the source must generate zero current.

The output of the current source charges capacitor C1 which in
conjunction with Unijunction Transistor (UJT) Q2 forms a relaxation
oscillator. As increasing voltages are applied to the control inputs,
the current supplied by Q1 increases causing C1 to charge more rapidly
thereby increasing the frequency of the oscillator.

The ramp waveform that appears across C1 is applied to the input of the
darlington emitter follower consisting of Q4 and Q11. The high input
impedance of this emitter follower is important in presenting
negligible load to the timing capacitor C1. A second emitter follower Q4
in conjunction with zener diode D3 performs a level shift so that the
ramp is transposed to slightly above ground potential while a third
emitter follower (Q5) provides a low output impedance buffer to couple
the signal to the rest of the waveforming circuitry.

The ramp waveform is used three ways. First, it is applied to the
voltage divider string consisting of R11, R24, R23 and R22. Between R11
and R24 the string is capacitively coupled through C5 directly to the
"RAMP" output jack J1 where it becomes available as a signal source.

Secondly, the ramp is applied to the Schmitt trigger composed of Q9 and
Q10. A Schmitt trigger has a low output or a high output depending on
whether the input voltage is above or below a pre-set design level. As
the ramp input to the trigger begins to rise the output remains low
until the voltage exceeds this level and then abruptly changes to the
high state. The output of the trigger, then, is a rectangular pulse at
exactly the frequency of the ramp input. By varying the amplitude of the
ramp you regulate the duration of the pulse by changing the relative
point at which the trigger changes state.

Finally, the ramp is applied to the input of the differential pair Q6
and Q7. In the differential configuration the voltage at the collector
of Q7 is in phase with the input ramp and the voltage at the collector
of Q6 is inverted. The diodes D1 and D2 "select the higher of the two
collector voltages and apply it to the base of emitter follower Q8.
During the lower half of the input ramp's excursion Q6's collector
voltage is higher and that section of the ramp is presented in an
inverted form to the base of Q8. There is a slight rounding at the
bottom of the wave during the cross over between Q6 and Q7 and a slight
pip at the top during the ramp "flyback" but neither of these
imperfections are audibly noticeable.

The most voltage sensitive portions of the circuit are powered from the
simple series voltage regulator consisting of zener reference diode D4
and pass transistor Q12. Less critical parts of the circuit are powered
by the decoupling networks R33/C6 in the positive supply line and
R35/C8 in the negative supply.

Danke,



Hello Don,

I made a LTspice model of the thing:

Version 4
SHEET 1 3144 724
WIRE 848 -320 -864 -320
WIRE 1008 -320 848 -320
WIRE 1472 -320 1008 -320
WIRE 1728 -320 1472 -320
WIRE 1888 -320 1728 -320
WIRE 2064 -320 1888 -320
WIRE 2496 -320 2064 -320
WIRE 2624 -320 2496 -320
WIRE 2912 -320 2624 -320
WIRE 848 -288 848 -320
WIRE 1472 -272 1472 -320
WIRE 1728 -272 1728 -320
WIRE 1888 -240 1888 -320
WIRE 2912 -224 2912 -320
WIRE -272 -144 -352 -144
WIRE -48 -144 -192 -144
WIRE 16 -144 -48 -144
WIRE 192 -144 96 -144
WIRE 304 -144 192 -144
WIRE 432 -144 304 -144
WIRE 592 -144 432 -144
WIRE 1008 -144 1008 -320
WIRE 1472 -144 1472 -192
WIRE 1520 -144 1472 -144
WIRE 1600 -144 1584 -144
WIRE 1632 -144 1600 -144
WIRE 1728 -144 1728 -192
WIRE 1728 -144 1696 -144
WIRE 2064 -144 2064 -320
WIRE 2496 -144 2496 -320
WIRE 2624 -144 2624 -320
WIRE 304 -96 304 -144
WIRE 848 -96 848 -208
WIRE 944 -96 848 -96
WIRE 1600 -96 1600 -144
WIRE 2000 -96 1600 -96
WIRE 2912 -96 2912 -144
WIRE 3024 -96 2912 -96
WIRE 192 -64 192 -144
WIRE 1472 -64 1472 -144
WIRE 1728 -64 1728 -144
WIRE 2912 -64 2912 -96
WIRE -48 -32 -48 -144
WIRE 1008 -16 1008 -48
WIRE 1184 -16 1008 -16
WIRE 1344 -16 1264 -16
WIRE 1408 -16 1344 -16
WIRE 1888 -16 1888 -160
WIRE 1888 -16 1792 -16
WIRE -544 0 -672 0
WIRE -352 0 -352 -144
WIRE -352 0 -464 0
WIRE -272 0 -352 0
WIRE 2064 0 2064 -48
WIRE 2160 0 2064 0
WIRE -112 16 -208 16
WIRE 1008 16 1008 -16
WIRE 2624 16 2624 -64
WIRE 2672 16 2624 16
WIRE 2768 16 2752 16
WIRE -272 32 -320 32
WIRE 432 32 432 -144
WIRE 848 32 848 -96
WIRE -864 64 -864 -320
WIRE -672 64 -672 0
WIRE 1344 64 1344 -16
WIRE 1472 64 1472 32
WIRE 1728 64 1728 32
WIRE 1888 64 1888 -16
WIRE 2064 64 2064 0
WIRE -320 80 -320 32
WIRE -48 80 -48 64
WIRE 368 80 -48 80
WIRE 592 80 592 -144
WIRE 2624 80 2624 16
WIRE 2912 80 2912 16
WIRE 192 112 192 16
WIRE 528 128 432 128
WIRE 1008 128 1008 96
WIRE 1104 128 1008 128
WIRE 2496 128 2496 -64
WIRE 2560 128 2496 128
WIRE 2768 128 2768 16
WIRE 2848 128 2768 128
WIRE 1008 160 1008 128
WIRE -48 176 -48 80
WIRE 128 176 -48 176
WIRE 1472 176 1472 144
WIRE 1600 176 1472 176
WIRE 1728 176 1728 144
WIRE 1728 176 1600 176
WIRE -864 192 -864 144
WIRE -672 192 -672 144
WIRE -672 192 -864 192
WIRE -480 192 -672 192
WIRE 848 192 848 96
WIRE 2496 192 2496 128
WIRE 1344 208 1344 144
WIRE 1600 208 1600 176
WIRE 1888 208 1888 144
WIRE 2064 208 2064 144
WIRE 2624 208 2624 176
WIRE 2912 208 2912 176
WIRE 2912 208 2624 208
WIRE -480 224 -480 192
WIRE -864 240 -864 192
WIRE -672 240 -672 192
WIRE 592 240 592 176
WIRE 784 240 592 240
WIRE 2768 240 2768 128
WIRE 2912 240 2912 208
WIRE -48 256 -48 176
WIRE 1008 256 1008 240
WIRE 1248 256 1008 256
WIRE 1008 272 1008 256
WIRE 592 288 592 240
WIRE 1248 352 1248 256
WIRE 2496 352 2496 272
WIRE 2496 352 1248 352
WIRE 1008 400 1008 352
WIRE 2768 400 2768 320
WIRE 2912 400 2912 320
WIRE -672 432 -672 320
WIRE -48 432 -48 320
WIRE -48 432 -672 432
WIRE 192 432 192 224
WIRE 192 432 -48 432
WIRE 848 432 848 288
WIRE 848 432 192 432
WIRE 1600 432 1600 288
WIRE 1600 432 848 432
WIRE -864 496 -864 320
WIRE 592 496 592 368
WIRE 592 496 -864 496
FLAG -320 80 0
FLAG 304 -96 0
FLAG -480 224 0
FLAG 1008 400 0
FLAG 1104 128 ramp
IOPIN 1104 128 Out
FLAG 2768 400 0
FLAG 2912 400 0
FLAG 3024 -96 pulse
IOPIN 3024 -96 Out
FLAG 1344 208 0
FLAG 1888 208 0
FLAG 2064 208 0
FLAG 2160 0 triangle
IOPIN 2160 0 Out
SYMBOL Opamps\\opamp -240 -48 R0
SYMATTR InstName U1
SYMBOL pnp -112 64 M180
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL res -176 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res -448 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 150k
SYMBOL cap -64 256 R0
SYMATTR InstName C1
SYMATTR Value 0.1ยต
SYMBOL 2N2646 144 112 R0
SYMATTR InstName U2
SYMBOL npn 368 32 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL npn 528 80 R0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL pnp 784 288 M180
SYMATTR InstName Q4
SYMATTR Value 2N3906
SYMBOL res 576 272 R0
SYMATTR InstName R4
SYMATTR Value 6.8k
SYMBOL res 832 -304 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL zener 864 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMBOL voltage -672 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL voltage -864 48 R0
SYMATTR InstName V2
SYMATTR Value 9
SYMBOL voltage -672 224 R0
SYMATTR InstName V3
SYMATTR Value 6.2
SYMBOL voltage -864 224 R0
SYMATTR InstName V4
SYMATTR Value 9
SYMBOL res 112 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 4.5k
SYMBOL res 176 -80 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL npn 944 -144 R0
SYMATTR InstName Q5
SYMATTR Value 2N3904
SYMBOL res 992 0 R0
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL res 992 144 R0
SYMATTR InstName R8
SYMATTR Value 500
SYMBOL res 992 256 R0
SYMATTR InstName R9
SYMATTR Value 1.68k
SYMBOL res 2480 176 R0
SYMATTR InstName R10
SYMATTR Value 4.7k
SYMBOL res 2480 -160 R0
SYMATTR InstName R11
SYMATTR Value 470k
SYMBOL npn 2560 80 R0
SYMATTR InstName Q6
SYMATTR Value 2N3904
SYMBOL npn 2848 80 R0
SYMATTR InstName Q7
SYMATTR Value 2N3904
SYMBOL res 2608 -160 R0
SYMATTR InstName R12
SYMATTR Value 10k
SYMBOL res 2896 -80 R0
SYMATTR InstName R13
SYMATTR Value 8.2k
SYMBOL res 2896 -240 R0
SYMATTR InstName R14
SYMATTR Value 1k
SYMBOL res 2752 224 R0
SYMATTR InstName R15
SYMATTR Value 47k
SYMBOL res 2896 224 R0
SYMATTR InstName R16
SYMATTR Value 100
SYMBOL res 2768 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R17
SYMATTR Value 100k
SYMBOL res 1280 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R18
SYMATTR Value 6.8k
SYMBOL npn 1408 -64 R0
SYMATTR InstName Q8
SYMATTR Value 2N3904
SYMBOL npn 1792 -64 M0
SYMATTR InstName Q9
SYMATTR Value 2N3904
SYMBOL res 1456 48 R0
SYMATTR InstName R19
SYMATTR Value 150
SYMBOL res 1712 48 R0
SYMATTR InstName R20
SYMATTR Value 30
SYMBOL res 1584 192 R0
SYMATTR InstName R21
SYMATTR Value 5.6k
SYMBOL res 1328 48 R0
SYMATTR InstName R22
SYMATTR Value 330
SYMBOL res 1872 48 R0
SYMATTR InstName R23
SYMATTR Value 680
SYMBOL res 1872 -256 R0
SYMATTR InstName R24
SYMATTR Value 3.9Meg
SYMBOL res 1712 -288 R0
SYMATTR InstName R25
SYMATTR Value 6.8k
SYMBOL res 1456 -288 R0
SYMATTR InstName R26
SYMATTR Value 6.8k
SYMBOL diode 1696 -160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL diode 1520 -128 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL res 2048 48 R0
SYMATTR InstName R27
SYMATTR Value 4.7k
SYMBOL npn 2000 -144 R0
SYMATTR InstName Q10
SYMATTR Value 2N3904
TEXT -288 112 Left 2 !.lib opamp.sub
TEXT -360 288 Left 2 !.tran 30m
TEXT 1816 408 Left 2 ;2720-2A model, some components guessed.

There was no mode for an UJT, so I made an 2N2646.

2N2646.asy:

Version 4
SymbolType BLOCK
LINE Normal 1 76 16 80
LINE Normal 1 85 1 76
LINE Normal 16 80 1 85
LINE Normal 48 88 48 112
LINE Normal 16 88 48 88
LINE Normal 16 96 16 16
LINE Normal 48 24 48 0
LINE Normal 16 24 48 24
LINE Normal 1 80 -16 64
WINDOW 0 93 35 Bottom 2
WINDOW 3 110 85 Top 2
SYMATTR Value 2N2646
SYMATTR Prefix X
SYMATTR ModelFile 2N2646.SUB
PIN -16 64 BOTTOM 8
PINATTR SpiceOrder 1
PIN 48 112 RIGHT 8
PINATTR SpiceOrder 2
PIN 48 0 RIGHT 8
PINATTR SpiceOrder 3

Model from the Net, probably by the late Jim Thompson:

..SUBCKT 2N2646 1 2 3
DE 1 4 EMITTER
VE 4 5 DC 0
HVE 6 0 VE 1K
RVE 0 6 1MEG
BBB 5 7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)
CBB 5 7 35P
*RB1 7 2 38.15 RMOD
*RB2 3 5 2.518K RMOD
*.MODEL RMOD R TC1=.01
RB1 7 2 38.15
RB2 3 5 2.518K
..MODEL RMOD R TC1=.01
..MODEL EMITTER D (IS=21.3P N=1.8)
..ENDS 2N2646

---

There are many components without types or values, so
I had to guess them.

There are plenty of issues, beginning with the slot in the
triangle at the positive tip, die to the retrun time of
the ramp signal.

The output capcitors are left out of the simulation, I do
not have a mode for a reversed electrolytic.

--

-TV