"DoN. Nichols" wrote in message
...
On 2017-03-17, Jim Wilkins wrote:
"DoN. Nichols" wrote in message
...

[ ... ]
The semiconductor test equipment maker I worked for pushed the
state
of the art and went through a lot of circuit board revisions as a
result. They used layout design rules too tight for the board
vendor
to consistently meet so internal shorts were an issue.

Oops!

I wasn't involved in board layout at that time. We sometimes found the
images of dust and hairs in the copper. The quality of high volume
production boards was better than the quick-turnaround prototypes. The
dreck could have been the company's own fault - they made at least
some of their artworks on a Gerber drum photoplotter in the same room
as the E-size diazo copy machine.

20A at 1V usually identified and cleared the short,

It could also clear a buried lead for multi-layer boards,
depending on cross-sectional area. :-)

Only a few techs were trusted to do it.


Fun! Was the board populated before you went short hunting, or
was it checked out first to determine whether there were shorts or
opens?

Both, IIRC. They ordered expensive GenRad bed-of-nails probe fixtures
to test stable releases but not prototypes.

The product line that had the problems was the digital memory tester
and I was mostly involved with analog IC testing, which didn't have
the wide address and data buses or high speed requirements. They
called me in when no one else could find a bug and then were annoyed
when my fresh eyes located it in 10 minutes.

That was in the first half of the 1980's. By the early 1990's the
PC
board vendors had substantially improved their process control and
I
had little trouble with shorts despite substantially tighter
spacing
rules. They gave me enough detail on the processes to know what I
could likely get away with at standard or higher cost, ie more
labor
and lower yield. I've seen a circuit board that cost the Air Force
$30,000 and heard of yields of 1 in 20 for high layer counts.

Ouch! $30K populated, or just the bare board?

Populated, carefully tuned and thoroughly tested. It was from an
aircraft radar.

For example the fiberglass threads deflect a fine drill bit and
determine the amount a pad has to be larger than the hole. They
don't
stack the boards as high on a small prototype order so I could use
smaller via pads than would be acceptable in production.

Solid carbide drills, or HSS? I know that the HHS ones in the
#70 size range were quite flexible, but the solid ones you even
bounce
too much light off one side and "plink". :-)

Carbide, on an Excellon machine. I wanted 0.019" (IIRC) vias after
plating, the smallest they could guarantee.The drill was smaller. The
design rule required a pad diameter of lets say 0.020" larger, which
blocks several possible routing channels. The goal was to have a
little copper left at the edge of the pad for the worst case of drill
bit misalignment, otherwise the hole wouldn't plate and wave-solder
properly. On hand-soldered prototypes I could fix it.


The size
of
the board also affects misalignment between the drill and the pads
due
to uncertain thermal expansion when they press the layers together.
Making power planes a lattice instead of solid and filling unused
spaces helped keep my multilayer boards flat, unlike some other
people's.

I've seen the latticed power planes and wondered why. One
thought was to minimize weight in avionics. I've even seen them on
plain double-sided boards -- no buried power planes..

Unconnected copper fill in unused areas of the board is there for the
same reason, to balance thermal expansion and contraction. The people
the board houses hire for layout aren't electrical engineers and the
best you can hope for is that they blindly follow the rules you give
them. They may misapply those mysterious sacred rules later, like on a
two layer board that isn't assembled in a hot press.
https://en.wikipedia.org/wiki/Pre-preg

The "PADS" PCB design program I used was complex and disorganized
enough to need a week or two to learn. The instructors often had no
clue about the electrical issues I asked them about, like RF tuning
stubs and guard rings that their software saw as errors.
https://offlogic.wordpress.com/2009/...ery-very-much/

I did the board outline and component placement for Segway's Balance
Sensor Assembly (gyro) because the design house complained that it was
too difficult.
http://www.rbokdesigns.com/summatives/segway/bsa.html#
The drawing doesn't show that some of the daughter boards with the
gyros on them are slanted, which made automated soldering tricky. The
BSA is shoehorned into the tight space between the motors.

I had to assemble boards another tech designed that were so dished
they would float. They had a nearly solid ground plane for RF filter
cans on one side and only the single traces connecting them on the
other. Unequal thermal contraction of the one-sided copper made them
cup as they cooled, concave on the copper side. They had to be
installed in an empty card cage so I could reach in and push the edge
connector straight.

I had been learning TIG in night school and soldered the
stack-of-dimes pattern around the filter cans.

When I encountered a similar situation later I asked the engineer to
use his patch antenna design program to model a controlled impedance
trace with both a ground plane under it and copper fill on either
side, and gave him the copper weight and thickness and dielectric
constant of the low-loss FR4 board material. It required a picket
fence of vias connecting the two ground plane layers on both sides to
come out to 50 Ohms.

...........
Hmm ... the MC6800 could be halted by the clock to stretch the
cycle for slower chips -- but the Altair 680b did not implement
that, so
the whole thing ran at 500 KHz instead of the proper 1 MHz to allow
the
1702A EPROMs used for the monitor.

The CPU could be halted as long as you wished by stopping the
clock -- no dynamic memory in it, and if you used static RAM as
well, no
problems.

The 8080 is dynamic internally and needs the clock running. It used
WAIT-READY handshaking to extend memory accesses as long as
necessary. A 900 KHz clock was enough for the memory samples the
engineers gave me. I put in battery-backed 6116s and then 2816 flash
ram for the monitor program. My goal was to prove that I'd learned to
design with the components instead of creating a useful computer,
although I did take it as far as writing an editor/assembler until the
8080's lack of relative jumps halted the project.

[ ... ]

Now Mitre could have been a more convenient place for me to
work. There was at least the octagonal mushroom building
belonging
to
them a lot closer to my home than Ft. Belvoir was. :-)

Mitre was a real country club, which is great for the golfers, not
so
much for the caddies attending to them. You weren't squat without
at
least an MSEE. I got by on the unusual breadth of my practical
engineering experience rather than its rather shallow theoretical
depth.

Hmm ... I would have had to do the same, then -- if I could.

Enjoy,
DoN.

Most of their electronic techs had the standard skill set, leaning
toward radio. I had to repeatedly prove I could do more.
-jsw