On 2016-09-05, Jim Wilkins wrote:
"DoN. Nichols" wrote in message
...

Ouch! Perhaps a buffer near the test head which could be
pre-loaded from the computer, and then triggered to spit it out at
the
RAM on command. If the tests were repetitive enough, that would
minimize the total bandwidth sent to the test head -- and local
checking
for errors and only spit the errors back to the computer to minimize
the
bandwidth the other way.

That was the era of the 2102 1K x 1 and 2141 4K x 1 static RAM, and
welding-sized power supplies for big (64K) banks of them.


There were 8 of the 2102s in my Altair 680b (kit computer based
on the Motorola 6800, not the Intel 8080 which the first Altair had).
While not too fast, they were still a lot faster than the machine,
simply because they pulled the clock down to 500 KHz instead of 1 MHz
(the max for the CPU chip) because they used 1702a EPROMs for the
monitor, and did not bother implementing a stretchable clock for the
system, so it had to be slowed down to the 1702a's speed. Otherwise, it
could have been 1 MHz -- or later, 2 MHz for the 6800B, which I
wire-wrapped into a replacement CPU card for the SWTP 6800 (moving the
baud-rate clock off the CPU board, because the original of that system
had something like a 768 KHz CPU clock to divide down to match baud
rates. :-) (I was also using the 6116s in that system at its end of
life. A lot more reliable than the dynamic RAM chips which were used on
some boards. So -- the replacement CPU board was wire-wrap too.

They had
samples of 6116 2K x 8 and 6264 8K x 8 CMOS static memory but IIRC
they weren't fast enough, so I was given them for my wirewrap 8080
computer. At first it had 256 bytes of memory.

Four of the 6264 chips would have saturated the address space of
the 6800. :-)

DRAM was still being developed. A few years later I designed an ASIC
controller for it.

I had fun diagnosing a problem with some Multibus RAM cards in
my first unix box -- based on the Motorola 68000. Turned out to be a
problem in a delay chip used to make the different clock pulses for the
dynamic RAM.

When they closed they had been trying to design ceramic hybrid pin
drivers to fit in the test head with some pattern memory on them.

Makes sense.

The test head contains the electronics that have to be close to the
probe card that contacts the IC bonding pads to test it while it's
still on the wafer.

Sure -- keep the waveshape clean for pulses fed to the chips,
and minimize delay for what comes back to test.

The head can't be too large or heavy to position
within a thousandth of an inch. It's the smaller box on the positioner
on the purple machine.
http://aesrep.com/STArATE.php

A pity that doesn't give closer views.

I've never been in a clean room to see these machines in use. The
wafer probing I did at Unitrode was all individual setups with
standard lab test equipment, with no dust control since we were
testing only prototypes. Wafers are brittle, but otherwise exposed ICs
are surprisingly resistant to damage.

Brittle, yes -- and static sensitive -- especially memory chips.
(For that matter, memory chips are also sensitive to illumination
levels.) I remember hobby articles using RAM chips without covers as
image sensors. :-)

Enjoy,
DoN.

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