"Random" Circuit Needed.
On Sun, 26 Apr 2015 12:58:31 -0400, krw wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman wrote:
On 4/25/2015 5:23 PM, John Fields wrote:
if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.
The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.
Shottky TTL is really DTL under the covers. D's aren't used much for
logic because (bipolar) Ts aren't either but DTL certainly isn't dead.
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Nice.
John Fields
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