On Sat, 25 Apr 2015 15:49:06 -0400, rickman
wrote:
On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman
wrote:
On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman
wrote:
On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman
wrote:
On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman
wrote:
On 4/16/2015 4:46 PM, John Fields wrote:
If you need the extra state, then even for huge counters the
practicality fades into insignificance.
John Fields
I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.
---
What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.
Can you post a contradictory example culled from the "larger field
of contenders" ?
I don't see where you have provided any examples to contradict.
---
I already posted a link to an 8 bit PRSG with 256 output states.
Did you miss it?
Apparently.
---
Well, then, for your perusal, here ya go:
https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0
This is hardly a "huge" counter...
---
Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.
Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.
---
As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie
presented.
In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.
---
Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.
A bunch of diodes? I guess so, but the speed issue still remains.
---
How so?
if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.
---
The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.
---
That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.
---
Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol
---
"State of the techniques"???
LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.
John Fields
Professional balloon pricker