On Thu, 16 Apr 2015 01:07:08 -0400, rickman
wrote:

On 4/15/2015 7:38 PM, John Fields wrote:
On Thu, 02 Apr 2015 17:20:47 -0700, Jim Thompson
wrote:

On Thu, 02 Apr 2015 18:52:57 -0500, John Fields
wrote:

On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

John Fields

smirk:-}

...Jim Thompson
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Amazing, isn't it?

Idiots with opinions post their garbage as if it was holy but post
no evidence to support their claims.

I don't know that Jim is an idiot,

---
The reference to idiocy wasn't pointing to Jim, it was pointed at
Betts.
---
but I'm not sure this formula is very
useful to implement in logic easily.

---
You echo my point.
---

The multiply is not too bad and
the addition is easy. But the modulo operation by 2^16+1 is downright
hard. I think that is why he is smirking. He knows this is not very
practical...

---
You have a remarkable grasp of the obvious.
---

BTW, I did a quick search to find the method of extending an LFSR to
cover the full range of 0 to 2^N values...

http://www.xilinx.com/support/docume...es/xapp052.pdf

Seems he detects the state with N-1 ones and inverts the output. So for
a 16 bit register this requires decoding 15 bits. But for small length
LFSRs this is very practical.

---
If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields