On Mon, 18 Nov 2013 10:30:05 -0800, John Larkin
wrote:
On Mon, 18 Nov 2013 11:14:39 -0700, Jim Thompson
wrote:
On Mon, 18 Nov 2013 09:34:16 -0800, John Larkin
wrote:
On Mon, 18 Nov 2013 09:05:54 -0700, Jim Thompson
wrote:
On Mon, 18 Nov 2013 06:59:03 -0800, John Larkin
wrote:
On Thu, 14 Nov 2013 08:13:54 -0700, Jim Thompson
wrote:
On Wed, 13 Nov 2013 19:30:07 -0800, John Larkin
m wrote:
On Mon, 11 Nov 2013 10:49:05 -0600, "Tim Williams"
wrote:
Is J2 the socket for the PIC, or is it going through cables to the PIC
somewhere else?
What are the trace lengths on the loop from Q1 source (ground), to the
nearest bypass capacitor on +12VR, through D5, back to Q1? (Hint: D5 must
be placed at Q1, not at the coil.)
Why? It will clamp a flyback overshoot wherever it is in the circuit.
If the wiring from FET to coil is significantly inductive, then what?
...Jim Thompson
Since you can't think this through, you'll have to Spice it.
No. It's _you_ who'll have to LTspice it... and you'll get it wrong
:-}
...Jim Thompson
Whenever "Thompson" and "inductance" show up in the same post, amusement is sure
to follow.
Wiring inductance _between_device_and_catch_diode_ can cause voltage
spikes, depending on device turn-off speed... irrespective of what
smug-ass comments Larkin may churn up.
...Jim Thompson
Show us.
See attachment. Sorry that Larkin is incapable of understanding the
basic behavior of _any_ inductance.
...Jim Thompson
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