On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs
wrote:
On 10/15/2012 9:16 PM, Nico Coesel wrote:
Jim Thompson
wrote:
Finally zeroing in on modeling the 74HC4046 after finding a
unpublished AppNote that gave more details on the innards. This is
what a fixed frequency looks like, simulation-wise...
http://www.analog-innovations.com/SE..._VCO_2_SIM.pdf
Comments? Scalings? (This is based on AppNote and Datasheets
claiming trip at VDD/2).
First release will be VCO only and will be in LTspice format. Once
you approve that, the PFD is virtually all logic.
Funny. I put a HC7046 into a design recently. Unfortunately there are
no design tools for calculating the loop filter components. So how
about modeling the HC7046? It is much more interesting because of the
lock detect output which can be used as a reset.
I investigated all the HC versions (HC4046 from several vendors, HC7046,
HC9046) about a year back, iirc, and their oscillators are all junk
compared with the ancient metal-gate 4046. They're horribly nonlinear,
all in different ways, which makes it really hard to build a good PLL.
What's worse, their oscillators quit when their control voltages are
within a volt or so of ground (the actual threshold for misbehaviour
varies from device to device).
The 7046 is enough more expensive that I'd be much happier spending the
dough on a better oscillator, and using the back end of a normal HC4046
from a good vendor.
Cheers
Phil Hobs
It occurs to me that the variable current input quits at about 1*VTH.
So you were trying to get to zero frequency ?:-)
Add some offset current and it won't quit oscillating.
...Jim Thompson
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