View Single Post
  #32   Report Post  
Posted to alt.binaries.schematics.electronic,sci.electronics.design
JosephKK JosephKK is offline
external usenet poster
 
Posts: 454
Default Okay, so, what am I missing here?

On Tue, 5 Jun 2012 22:12:30 -0400, "Tom Del Rosso"
wrote:


Jim Thompson wrote:
On Tue, 5 Jun 2012 18:28:22 -0400, "Tom Del Rosso"
wrote:


Jim Thompson wrote:
On Wed, 23 May 2012 15:40:17 -0500, "Dave"
wrote:

Posted a while back about a project I am trying to concoct- an
intercom for my front door- and have made some progress.
Unfortunately I hit a speed bump when I added transistor Q4.
Now it only gives me noise at the output, and lots and lots of
that. Capacitors are all 100uF 35V, which I am thinking may be
the problem (maybe the last couple need to be 50 or 75V?)
Originally thought I might be overdriving Q4, so I replaced it
with a 2N5296 from my junkbox, but that just doubled the volume
of the noisy output. If anyone sees something I should but
don't, please post. The only thing I can think of is upping the
voltage on C8 and C9.

Any help is *greatly* appreciated...

Dave


Back up and do a little math. Calculate the bias current in that
last stage. (In fact, calculate all your stage biases.)

In my head, it's 14ma. That can't be right. The calc concurs. Is
that a little bit too much?

Aren't the emitter caps about 10 times as big as needed?

Ian did notice that he was just throwing gain at the problem though.


Yep, I was stunned... Ian said something cogent. But his buddy, Dave,
is beyond all hope... rude little POS.


I don't have AoE in reach, but I don't think they mention bias current in
their approach to design. They approach it with the rule of thumb that the
input impedance should be 10x the output impedance of the previous stage.
Similar. (The input impedance of the OP's stages are only slightly higher
than the previous output impedance.)

I'd like to know if you use any rules of thumb for this sort of thing. Or
is everything just optimized by multi-variable calculus?


Well, i know of two ways to design multistage transistor amplifiers:
One starts at the beginning and starts with the required/desired input
impedance. That sets up the bias network and then the rest falls out
rather naturally. If the output voltage/current/impedance does not work
yet add another stage.
The second starts at the output requirements and proceeds to the input
requirements.
If there is noticeable excess gain in the system you can retune the stages
(with an eye toward reducing cost) or add global feedback. Global
feedback after three stages is rather risky.

?-)