On Sun, 11 Mar 2012 12:59:31 -0700, John Larkin
wrote:

On Sun, 11 Mar 2012 12:47:30 +0100, "petrus bitbyter"
wrote:


"John Fields" schreef in bericht
. ..
On Mon, 05 Mar 2012 19:31:23 -0800, John Larkin
wrote:

On Mon, 05 Mar 2012 17:51:35 -0600, John Fields
wrote:

On Mon, 05 Mar 2012 09:33:16 -0800, John Larkin
wrote:


Consider this: the comparator output is low, so CE is true into U6.
U6 and U2 are happily counting clocks.

Suppose the U6 count is 0xF, and U2 is 0x4. U6 carry out is true (low)
into U2. The correct next count would be Ox0 and 0x5, which is 80
counts decimal.

Now let the comparator output go high, so U6 no longer sees a true
carry input. But it takes a while before the "don't count" Cout/Cin
signal propagates out of U6 into U2. Clock it then. U6 doesn't count,
but U2 does. The next state is U6 = 0xF, U2 = 0x5, 95 decimal, which
is bad wrong. Classic carry chain error. U9+U7 have the same issue.

---
True enough, but what you've missed is that what happens with U2 and
U6 when the comparator goes high doesn't matter, since the
comparator's going high generates a high-going pulse out of U3 which
loads the contents of U2 and U6, at that moment, into U9 and U7.

"At that moment?" Wrong yet again. The PE from U3 to U7/U9 is 1.4 us
wide, and it's an async DC jam load. When U6 and U2 count wrong, as
noted above, the bad count is settled after a typ delay of 200 ns
after the clock, and that's what gets loaded into U7/9.

It's a hairball. You don't get hazards like this in a clocked
synchronous system.

---
Apparently, what you've missed is that carry out is synchronous.


--
JF

This counter is an example of a so called Mealy machine which means that at
least one of the outputs depends on both the current state an one or more
input signals. The carry_out is such an output. It depends on the current
state, the carry_in and the up/down. So as long as these last two signals
are synchronous, the carry_out signal will be synchronous as well, otherwise
you have to make sure that the inputs are stable some setup time before the
next active clock edge. If not, the counter may fail to count correctly.

petrus bitbyter


Cin to U6 and U9 are both asynchronous, which makes their carry outs
async too, so there are hazards.

There's no reason to create hazards like this.

---
Clearly, you don't understand the 4516's carry circuitry, and are
making a fool of yourself by pretending you do by tilting at
windmills.

--
JF