"John Larkin" schreef in
bericht ...
On Thu, 08 Mar 2012 09:50:25 -0700, Jim Thompson
wrote:

On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin
wrote:

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.


Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.


Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson


That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

VHDL is not an analysis language, it's a logic description language.
Actual gates and flops are synthesized downstream, with other tools,
and may look very different from the VHDL when it's actually mapped
into specific hardware.

There are VHDL simulation programs, but they usually work from the
VHDL itself, not the synthesized logic. What we usually do is sim at
VHDL level and do static timing analysis (which is ignorant of the
logic intent) after logic synthesis, and hope that the logic synthesis
stuff worked.

One could write an async logic design in VHDL - just don't clock
anything - but I don't know where you'd go from that, or how you'd
verify the final logic. Sounds like a nightmare, which is why nobody
has got it to work very well.


--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

Down at the transistor level it's all analog. The combinatorials like the
gates can be considered analog and simulated that way but there's hardly a
thing to gain. Once you're using feedback building fliplops and other
sequential elements, analog simulation become more difficult though not
impossible. At this level the elements are still asynchronous but can be
used to build synchronous circuits. You can bet, the logic diagrams of the
internals of synchrounous counters and the like (hopefully) describe the
function, not the internal design. (Which is not uncommon in analog circuits
as well.) I'm not certain to what limit you can use analog simulation for
digital circuits these days, but it's clear that even a simple small micro
cannot be simulated this way. I heard rumours last year about design
software to build asynchronous sequential circuits, faster then the
synchronous counterparts, but I couldn't find it and the rumour died.

petrus bitbyter