View Single Post
  #29   Report Post  
Posted to alt.binaries.schematics.electronic,sci.electronics.design
John Larkin John Larkin is offline
external usenet poster
 
Posts: 1,420
Default ZCD with no Dflops

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.



Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.


Stay tuned...


Can't wait.


I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson



That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation. Imagine simulating an analog circuit that has a billion
transistors and thousands of inputs and outputs. Now do that over Vcc
and process variations and temperature.


--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators