On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
wrote:
On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
wrote:
[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.
Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.
Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.
Stay tuned...
Can't wait.
I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.
...Jim Thompson
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