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John Larkin John Larkin is offline
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Default ZCD with no Dflops

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
wrote:

On Tue, 06 Mar 2012 08:50:12 -0800, John Larkin
wrote:

On Tue, 06 Mar 2012 08:58:27 -0600, John Fields
wrote:

On Tue, 6 Mar 2012 01:22:33 +0100, "petrus bitbyter"
wrote:


BTW. Although the circuit may do for the project at hand, I wonder why so
many people spend so much time on an obsolete circuit.

---
It's just for "fun"; a response to a challenge from John Larkin to
start a discussion by posting an original circuit for a zero-crossing
detector.

Looks like it worked!


It did; at least you tried. And it is a nice illustration of the
many-layered hazards of haywire async logic design.


---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.



Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.


Stay tuned...


Can't wait.


--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

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