On Mon, 05 Mar 2012 09:33:16 -0800, John Larkin
wrote:


Consider this: the comparator output is low, so CE is true into U6.
U6 and U2 are happily counting clocks.

Suppose the U6 count is 0xF, and U2 is 0x4. U6 carry out is true (low)
into U2. The correct next count would be Ox0 and 0x5, which is 80
counts decimal.

Now let the comparator output go high, so U6 no longer sees a true
carry input. But it takes a while before the "don't count" Cout/Cin
signal propagates out of U6 into U2. Clock it then. U6 doesn't count,
but U2 does. The next state is U6 = 0xF, U2 = 0x5, 95 decimal, which
is bad wrong. Classic carry chain error. U9+U7 have the same issue.

---
True enough, but what you've missed is that what happens with U2 and
U6 when the comparator goes high doesn't matter, since the
comparator's going high generates a high-going pulse out of U3 which
loads the contents of U2 and U6, at that moment, into U9 and U7.

Then, later on, when the comparator goes low again, the carry inputs
of both counters will be enabled, U2 and U6 will start accumulating
new clocks, and U9 and U7 will time out and provide the divide-by-two
pulse at the zero crossings.

--
JF