On Sun, 04 Mar 2012 09:20:48 -0800, John Larkin
wrote:

On Sun, 04 Mar 2012 11:01:04 -0600, John Fields
wrote:

On Sun, 04 Mar 2012 07:27:18 -0600, Lasse Langwadt Christensen
wrote:

John Fields wrote:
On Sat, 03 Mar 2012 20:18:46 -0800, John Larkin
wrote:

On Sat, 03 Mar 2012 16:24:01 -0600, John Fields
wrote:

Yikes, the PEs are completely asynchronous to the clock.

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Yup, that's how they're designed to be.

sorta...

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There's all sorts of available pathologies.

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None that I can see; peruse:

http://www.ti.com/lit/ds/symlink/cd4516b.pdf

for a clue.

--
JF

It might not matter, but when you have PE async to the clock
you will at times violate one of the specs on the first page
preset removal time

-Lasse

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From figure 3, since the external clock is gated with PE and the
internal clocks forced high while PE is asserted, the state of the
external clock during load time doesn't matter.

You're right in that if PE is de-asserted and the external clock goes
high too soon after PE goes low, the Preset Enable Removal Time spec
will have been violated, but I think (since all the presets have
already been loaded and are stable) all that'll happen is that
there'll be a delay until the next clock high comes along before the
counter starts counting.

It does violate the requirements on the first page of the data sheet,

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The point, which you missed, is that it doesn't matter.
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but maybe you know more about the internals of these parts than the
designers did.

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Straw man.
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The asynchronous CE hazard is much worse.

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You don't know what you're talking about.

--
JF