On Sun, 04 Mar 2012 13:48:00 -0800, John Larkin
wrote:

On Sun, 04 Mar 2012 13:58:13 -0700, Jim Thompson
wrote:

On Sun, 04 Mar 2012 12:44:53 -0800, John Larkin
wrote:

On Sun, 04 Mar 2012 11:23:24 -0700, Jim Thompson
wrote:

On Sun, 04 Mar 2012 09:14:57 -0800, John Larkin
wrote:

On Sun, 04 Mar 2012 04:13:51 -0600, John Fields
wrote:

On Sat, 03 Mar 2012 20:18:46 -0800, John Larkin
m wrote:

On Sat, 03 Mar 2012 16:24:01 -0600, John Fields
wrote:

Yikes, the PEs are completely asynchronous to the clock.

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Yup, that's how they're designed to be.
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There's all sorts of available pathologies.

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None that I can see; peruse:

http://www.ti.com/lit/ds/symlink/cd4516b.pdf

for a clue.

Clue, like reading the table on the first page of the datasheet? Clue,
like looking at the internal logic diagram?

You are violating the setup and hold times specs for both PE and CE
inputs, and doing that across cascaded chips to boot. This *will*
screw up, and won't take long to do it... just long enough to be a
maddening intermittent failure.

Next thing you'll be claiming is that you designed this horrible
asynchronous mess on purpose to annoy people.

Well? You certainly seem annoyed. And look at all the time Fields
has caused you to waste ;-)

...Jim Thompson

Not more than a couple of minutes; the data sheet is pretty simple.

So, you approve of JF's design here?

Nowhere have I said that, have I?

No, you are careful to not commit one way or the other. If you say
they're good, you'll be lying *and* look like a fool. If you say
they're bad, you'll be betraying a fellow hen\\\ ally.

The best you've done is suggest that he's posting crap on purpose.
Pretty bad compromise.

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Ha ha!

Jim didn't take your bait so you got your knickers all in a bunch? :-)

Better take it easy or you'll be going apoplectic soon.

--
JF