ZCD with no Dflops
On Mon, 05 Mar 2012 03:27:42 -0600, John Fields
wrote:
That means that from the time the high-going clock edge which drives
Carry Out low occurs, the next high-going clock edge must occur after
480 + 200 + 130 = 810ns elapses.
Since my clock is 50µs wide, I don't see much of a problem meeting
that criterion, do you?
---
Oops... 20µs.
Still no biggie.
--
JF
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