On Sun, 04 Mar 2012 09:14:57 -0800, John Larkin
wrote:

On Sun, 04 Mar 2012 04:13:51 -0600, John Fields
wrote:

On Sat, 03 Mar 2012 20:18:46 -0800, John Larkin
wrote:

On Sat, 03 Mar 2012 16:24:01 -0600, John Fields
wrote:

Yikes, the PEs are completely asynchronous to the clock.

---
Yup, that's how they're designed to be.
---

There's all sorts of available pathologies.

---
None that I can see; peruse:

http://www.ti.com/lit/ds/symlink/cd4516b.pdf

for a clue.

Clue, like reading the table on the first page of the datasheet? Clue,
like looking at the internal logic diagram?

---
Yeah, you got it!

That, plus learning to read the 4516 timing diagram on page 3-253
would be a good start.
---

You are violating the setup and hold times specs for both PE and CE
inputs, and doing that across cascaded chips to boot. This *will*
screw up, and won't take long to do it... just long enough to be a
maddening intermittent failure.

---
Well, let's see...

Since they're asynchronous, there are no setup and hold times for the
PE inputs, only a minimum pulse width which, with a Vcc of 5V, is 220
ns, according to the table on page 3-249.

My PE input pulses for both the up and down counters are about 1µs
wide, which is well within spec.

There is a Release Time spec, though, (150ns) which defines how much
time must elapse between PE going low and the clock's next high-going
edge starting the count.

That spec will be violated if that time is less than 150ns - which
will happen in my circuit - but the only penalty that'll be paid is
that the counter won't 1ncrement/decrement until the next rising edge
of the clock; no big deal as far as my circuit is concerned.

As for the Carries, there's a maximum delay of 480ns from clock to
Carry Out of the first stage, a transition time of 200ns for the Carry
Out, and a setup time of 130ns for the Carry In of the second stage,

That means that from the time the high-going clock edge which drives
Carry Out low occurs, the next high-going clock edge must occur after
480 + 200 + 130 = 810ns elapses.

Since my clock is 50µs wide, I don't see much of a problem meeting
that criterion, do you?
---

Next thing you'll be claiming is that you designed this horrible
asynchronous mess on purpose to annoy people.

---
Only a "horrible asynchronous mess" to asynchyrophobes who can't
appreciate elegant timing and who use clock edges as crutches.

--
JF