On Sun, 04 Mar 2012 04:13:51 -0600, John Fields
wrote:

On Sat, 03 Mar 2012 20:18:46 -0800, John Larkin
wrote:

On Sat, 03 Mar 2012 16:24:01 -0600, John Fields
wrote:

Yikes, the PEs are completely asynchronous to the clock.

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Yup, that's how they're designed to be.
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There's all sorts of available pathologies.

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None that I can see; peruse:

http://www.ti.com/lit/ds/symlink/cd4516b.pdf

for a clue.

Clue, like reading the table on the first page of the datasheet? Clue,
like looking at the internal logic diagram?

You are violating the setup and hold times specs for both PE and CE
inputs, and doing that across cascaded chips to boot. This *will*
screw up, and won't take long to do it... just long enough to be a
maddening intermittent failure.

Next thing you'll be claiming is that you designed this horrible
asynchronous mess on purpose to annoy people.


--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

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