"Jim Thompson" schreef
in bericht ...
An XOR is a convenient structure to allow a control signal to invert
or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while
non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson
--
| James E.Thompson, CTO | mens |
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| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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I love to cook with wine. Sometimes I even put it in the food.

I think it's an analog problem rather then a logic one as logic does not
dive below gate level

A quick look makes me think the problem is caused by the input signals that
are to be inverted (3 stage) or not (2 stage). The old TTL chips provided
"complementary output elements", the SN74265. Using this elements instead of
normal inverters will provide 3 stage delays all the time.

petrus bitbyter