Robert Baer wrote:
John Larkin wrote:
On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series
resistor to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple
in the 2800V supply shows across the DUT (10Meg resistor used for
analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a
constant current instead.
Useful comments please?

The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.
It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John



I tried removing the 4.7uF cap as it seemed "obvious", and not only
did the ripple current get worse, there were more power line harmonics.
I tried a 4700pF cap across one of the 100Meg resistors ("bottom"
one), to no avail so i quit that nonsense.
I tried a 4700pF cap across the supply and that reduced the ripple
some - not a lot. Large value 3KV caps are not exactly common, small or
inexpensive. Looks i would need a cap in the region of 1uF..

I came up with a better way of driving the FETs; all i need is a 500KC
oscillator with RMS output near input voltage - say oscillates from 1V
to 5V in.
See attached PDF.

OOPS! See a big goofus (me); the top 2 drivers are shorted - should
go from the source too the gate..
Perhaps with a better gate drive, removing C2 would be a benefit.