John Fields wrote:
On Thu, 21 Oct 2010 15:01:42 -0700, Jim Thompson
On Thu, 21 Oct 2010 08:13:45 -0500, John Fields
On Wed, 20 Oct 2010 15:45:35 -0700, Jim Thompson
On Wed, 20 Oct 2010 17:23:54 -0500, John Fields
On Wed, 20 Oct 2010 14:34:38 -0700, Jim Thompson

I'd like to conjure up a random bit generator.

Just feed it a clock and have it generate random bits.

74HC... components preferred... I have most everything in that family
in my parts bin ;-)

Whoopeee!!!

Right up my alley!

Do you want truly random or pseudorandom, and if pseudorandom how long
do you want the output to be before it repeats?

Pseudo-random is just fine. I just need it to test an
encoding/decoding chip design. A hundred bits or so before repeat
would be quite adequate. No security involved... just testing to be
sure of no decoding hiccups.


[ASCIImatic snipped]

The diodes and the inverter make a 7 input NOR which keeps the thing
from latching up, ever, and gives you all 256 states from 00 to ff.

I'm only getting 52 before a repeat :-(

(I'm looking at the serial stream.)

Strange.

Those taps are supposed to yield a maximal length sequence (2^n-1),
and the pulse-stuffer is supposed to force the sequence to include the
lockup state, yielding 2^n states between repeats.

I'll get on it tomorrow and, hopefully, find where the problem lies.

In the meantime, I apologize for the inconvenience.

Do I dare mention Don Lancaster's TTL Cookbook? He's got schematics up to
some fairly long length - I don't recall off the top of my head how long,
but it's definitely more than 16.

Cheers!
Rich