I'd like to conjure up a random bit generator.

Just feed it a clock and have it generate random bits.

74HC... components preferred... I have most everything in that family
in my parts bin ;-)

How random do you need it to be?

If you want truly or statistically-close-to-really random, it's a Hard
Problem. You'd probably want something like an avalanche or other
noise diode, amplified, and then fed into a comparator... shield and
filter the bleep out of it to keep it from being pulled around by
external noise. Latch the output of the comparator on each clock
pulse and you've got reasonably random bits.

If you're willing to accept pseudo-random bits (chaotic-looking, but
actually predictable), a cheap and easy solution is a maximal-length
linear feedback shift register. These require a shift register of
suitable width (feel free to daisy-chain several 74HC595 or similar)
and an N-input XOR. You simply XOR several of the parallel outputs of
the shift register together and feed this back into the shift-register
inputs. If you pick these tapped outputs correctly (creating a
primitive polynomial mod 2), the output bitstream will have a period
of 2^N-1 before it repeats (where N is the width of the shift register).

You have to be careful to pre-load the register with at least one "1"
bit at reset time... it'll stick at zero, otherwise.

Schneier's "Applied Cryptography" has a table of suitable primitive
polynomials on pages 376-377. Some of them are rather huge... if you
want a 3217-bit shift register version, he's got two of them!

There are several which would be pretty easy to implement, and have a
good long repeat period... 60 to 64 bits, with at most 5 inputs to the
XOR.

For more sophisticated LFSRs, you can:

- Run several of them of different lengths (each with its own feedback
chain), and XOR the results.

- Use an "alternating stop and go" generator, which uses three LFSRs
of different lengths and feedback taps. One generator "A" is
shifted on every clock; its output controls which of the other two
"B" and "C" is shifted during that clock; the final output is
taken by XORing the output bits of "B" and "C". This architecture
has the effect of "hiding" the raw outputs of the LFSRs from
visibility, and makes determining the LFSR feedback coefficients
quite a bit harder.

--
Dave Platt AE6EO
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