On Sun, 21 Feb 2010 11:41:49 -0700, Jim Thompson
wrote:

On Sun, 21 Feb 2010 10:15:31 -0800, mike wrote:

Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells more
snow for you), I was amusing myself trying to behavioral model a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage regulator
for general use, only those inside ASIC's where I can control all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or below VDO.

I'm guessing that output voltage drops linearly with VIN once the
drop-out point is hit??

But what about current capability? Does it drop sharply, linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!

Thanks!

...Jim Thompson

What are your assumptions about the source?
A battery going flat might induce limit-cycle oscillations
that wouldn't show up with a stiff source?? or not...

From my modeling point of view, the "source" is just "something"
connected to the "IN" terminal.

BUT, The way I am envisioning the model, a flaky source, if you have a
model for it, would induce the very behavior you want to see.

Maybe model "source" as a voltage source with a parameterized
impedance rise?

Or get out a battery manual and model "Charge", a parameter that
reflects both voltage and impedance effects?

...Jim Thompson


Overlay multiple un-synched signals to create a psuedo-random average
modulation 'noise' in the drive signal that can be amplitude modulated to
mimic anomalous source events.