pimpom wrote:
Jim Thompson wrote:
This rainy afternoon (East-coasters beware, that usually spells
more
snow for you), I was amusing myself trying to behavioral model
a
voltage regulator when you hit drop-out.

Then I realized, I've never designed an integrated voltage
regulator
for general use, only those inside ASIC's where I can control
all the
conditions.

Thus I'm clueless of behavior of commercial offerings at or
below VDO.

I'm guessing that output voltage drops linearly with VIN once
the
drop-out point is hit??

But what about current capability? Does it drop sharply,
linearly, or
linearly to some critical point then drop like a rock.

Pointers/data appreciated!


I haven't done an in-depth study either, but I know that the
output voltage drops in an approximately linear manner down to a
certain level of Vin. I've observed input ripple reproduced
linearly at the output. I expect that behaviour below a critical
Vin level will be design-specific and will be hard to predict
without careful analysis. The critical level would be reached
when active devices can no longer be biased in the active region.

I know even less about their actual behaviour regarding current
capability, but I do know that they do not drop sharply right
after dipping below Vdo. All this is assuming that we're talking
about common linear regulators like the 78xx series.


.... and LDOs are real bitches; talk about how to build an oscillator -
just design an amplifier.