See also: PCI-E. Supposedly, at insane data rates (real circuit bandwidth
1GHz), even if signal quality can be managed, propagation skew between bus
lines is ever more difficult (have you seen all the squiggles on a
motherboard between processor, northbridge and RAM?). So why not skip bus
width altogether, crank the clock rate (pushing circuit bandwidth even more
though), and use multiple asynchronous channels. The advantage lies in
clocking each stream at its own rate, rather than clocking 32 or 64 bits at
an identical rate. Bytes could arrive out-of-order, but buffering done
on-chip is a lot faster than a maze of wires on-board.

Tim

I've got no argument with what you're saying. There's are newer bus
technologies in the works but until a serialized processor comes out,
what's the point of switching to serial peripherals? If the processor
is outputting parallel data lines and has to be addressed in the same
way, why not deal with the race conditions of the parallel busses?

I'm having a major headache right now trying to adapt an LG
Electronics optical drive to an older Intel ICH4 SATA controller.
IMHO, Intel released the controller long before it was workable. Even
the next generation, ICH5, was limited in structure. It allowed for 2
PATA controllers and a SATA controller with the provision that all
could not be used together. Intel did not make them BIOS selectable
because they knew certain combinations could be disasterous. So they
left the configuration up to the OS manufacturer.

Thanks!! Now I can't get information from Intel, Silicon Image,
Microsoft or LG Electronics. They dump this crap on you with the spin
that they are new technology and will improve things. When I heard
that about twisted-pair technology, I nearly crapped. People bought
into it, some thinking twisted pair had suddenly become superior to
coax, just because they twisted it better. Anyone believing that has a
serious issue with technological understanding, like the fatbytestard.