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Franc Zabkar Franc Zabkar is offline
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Default Monostable made from OR gate and CR network , pulse duration ??

On Sun, 23 Nov 2008 13:48:53 -0800 (PST), Graham
put finger to keyboard and composed:

Ok ... Well this birds nest is about 35 years old , your right on the
'tricks' bit , there is more than one set of discreat 'cr's' on the
board ,

I did the same calculation , with the long 'cr' time the vlaues given
may be attached to the device thats making a 0.125 uS pulse (measured
on teck-t 500 mhz dig scope)

CR = approx 62% full charge voltage, (5 volts) so i assume the devices
are toggeling at the zero to logic 1 transission voltage of the
chip ...which is less than 50% rail .... so its going over early ...


I calculate that the threshold must be 1.14V. The range from 0.8V to
2.0V would be TTL limbo, at least for the SN74LS86 device I referred
to in my earlier post.

- Franc Zabkar
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