On Sat, 17 May 2008 22:39:43 -0700, "RST Engineering \(jw\)"
wrote:



The top dielectric layer is 12 mils, so a 50 ohm trace is only 20 mils
wide.

My calculator says 22 mils at one Gig, and not knowing your frequency of
operation puts me at somewhat of a disadvantage. I wonder if the mismatch
between 20 and 22 is honking things up.

It's wideband, DC to maybe 2.5 GHz, corresponding to roughly 150 ps
edges. I don't want something as simple as the pcb degrading what the
circuit can do, hence the desire to keep the traces very short. That
beats spending $1000 or so on better boards. Things are not yet honked
up; the board hasn't even been built.


That's cheap to fab from a quick proto house, but not optimum
for losses. I want this thing to have a risetime below 150 ps, and an
inch of 50 ohm line on this cheap crud is about 70 all by itself.

Let me understand, please. I'm having a hard time relating line matching to
risetime. What does the loss tangent of the material or dielectric constant
have to do with risetime?

Dielectric and copper losses gobble up high frequency components, so
naturally degrade the risetime of pulse leading/falling edges. I
suspect that, with 20 mil, 50 ohm lines, the copper skin loss is worse
than the dielectric loss. Added bummer is that they crud up the bottom
of the copper ("black oxide" process) to make it bond to the laminate
better, and that radically worsens skin losses. Most of the current is
headed down, so the shiny top side, working against air, doesn't help
that much.

Of course, impedance mismatches degrade risetimes too.




FR4 seems to have an Er around 4.5 at GHz speeds. Effective epsilon
for the microstrip is about 3.3.

I show 3.1, but that's picking at nits.

I'm using Appcad. If it has any systematic trend, it seems to design
traces that come out a bit lower impedance than intended. But then
most of the board houses take liberties with stackups too.

John