DIYbanter - View Single Post - Is S.E.D actually sci.electronics.DUMMIES ??

Jim Thompson

On Mon, 12 Mar 2007 17:14:30 GMT, "colin"
wrote:

"Jim Thompson" wrote in
message ...
On Mon, 12 Mar 2007 17:00:54 GMT, "colin"
wrote:

"Jim Thompson" wrote in
message ...
On Mon, 12 Mar 2007 16:32:05 GMT, "colin"
wrote:

"Jim Thompson" wrote in
message ...
Is S.E.D actually sci.electronics.DUMMIES ??

When I saw this original post....

From: "powerampfreak"
Newsgroups: sci.electronics.design
Subject: Somebody explaining this design?
Date: 9 Mar 2007 12:08:35 -0800
Organization: http://groups.google.com
Lines: 11
Message-ID: .com

I commented, "Looks like crap to me ;-)"

The response from the hot air crowd, you know, the ones posing as
guru's, was an implication that I was incorrect.

So I posed a simple question... do a hand analysis of the gain of the
circuit.

It's a simple analysis (if you're not a faker :-)

It's been about 40 hours since I posted that request/taunt.

Nary a peep.

So I think this is TRULY...

sci.electronics.DUMMIES ;-)

I'd not noticed that post till now when I had to go search for it,
I dont look here for a few days sometimes,
I could end up spending most of the day reading and answering posts
here,
wich I feel like ive ended up doing on a few occasions,
It amases me how the likes of Win and several others make so many posts
wich
go into such detail,
maybe they read/think/type a lot faster than me ?

but this looks like a piece of pie to me,
the input stage is just a differential pair made with Sziklai darlington
the rest is just taking the ratio of the right resistors .... there
easy
as
cake.

Colin =^.^=

So write an equation. Then the defect/poor-"design" will be obvious.

Wel ok if you insist, im kinda busy with my lightspeed converter so il
just
give it a quick going over,
in the first stage ignoring emitter resitance as its a darlington,
current is due to the input voltage apearing accros the resistance between
emitters,
wich is (r2+r6) in parallell with (R9+vr1)
this current flow through the collector load
consisting of (r4+r8) in parallel with (R10,R11)
and produces a voltage - good old ohms law again,
this differential voltage is amplified by the op amp stage in the ratio of
its feedback resistors,
ie r13/r10. to produce a single ended op voltage.

see - its just a question of resistance ratios.
now when do I get my pie or cake ?

Colin =^.^=

So write it as a single equation. You're waffling ;-)

jeez, you want me to expand out simple ohms law and stuff ?
...
ree = 1/(1/(r2+r6)+1/(r9+vr1))
rcc = 1/(1/(r4+r8)+1/(r10+r11))
gain = rcc/ree * r12/r11

I should of just said the gain is 42 that would of been easier,
ot would probably be right for some value of vr1 too !

Colin =^.^=

Write down A SINGLE EQUATION showing that the gain is "42" ;-)

...Jim Thompson
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