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Default Omndiagonal Serialization and Monitor Design

Hello, all.

Hell, J. Clarke, Tim, Keith, Joseph, DoN, Lew, Jasen, and James, in
particular.

ftp://users.aol.com/DGoncz/Publications/1152x864B.gif

shows a slightly modified version of the redefinition in the referenced
post, but this seems to be a more correct timing calculation. Here is
the modeline and associated information:

(Monospaced Font as before)

PowerStrip timing parameters:
1152x864=1152,0,8,0,864,0,1,1,60268,0

Generic timing details for 1152x864:
HFP=0 HSW=8 HBP=0 kHz=52 VFP=0 VSW=1 VBP=1 Hz=60

VESA detailed timing details:
PClk=60.27 H.Active=1152 H.Blank=8 H.Offset=-16 HSW=8 V.Active=864
V.Blank=2 V.Offset=0 VSW=1

Linux modeline parameters:
"1152x864" 60.268 1152 1152 1160 1160 864 864 865 866 +hsync +vsync

Now you must understand this is designed to be displayed *diagonally*!
The second active pixel in the first scan line will show, with the
correct deflection waveforms, at screen coordinates (2,2), using a 1
basis for the origin in the upper left, that is, an origin of (1,1). I
have not checked common factors for this "mode".

Doug Goncz
Replikon Research
Falls Church, VA 22044-0394