For those of you who read the "slightly misbehaving switchers" thread (which
has long since scrolled off my news server), I've had the chance to take a
look at the behavior of the switcher in question now that it's on an 8-layer
board with a ground plane. I've attached the results in the same format as
the original document. The Reader's Digest version of the results seems to
be... "nothing much has changed" -- there's still noticeable jitter in the
duty cycle with input voltages around 3V.

In any case, since the original (2-layer PCB) ended up working OK, I'm not
particularly worried about this (even though I wish the jitter weren't there
and don't really understand what causes it), I just wanted to share the
results with everyone helped on with the original problem.

---Joel

Joel Koltner wrote:
For those of you who read the "slightly misbehaving switchers" thread (which
has long since scrolled off my news server), I've had the chance to take a
look at the behavior of the switcher in question now that it's on an 8-layer
board with a ground plane. I've attached the results in the same format as
the original document. The Reader's Digest version of the results seems to
be... "nothing much has changed" -- there's still noticeable jitter in the
duty cycle with input voltages around 3V.

In any case, since the original (2-layer PCB) ended up working OK, I'm not
particularly worried about this (even though I wish the jitter weren't there
and don't really understand what causes it), I just wanted to share the
results with everyone helped on with the original problem.


Certainly doesn't look normal. Did you ever contact LTC about it?

I am not a particular fan of PWM chips with integrated power devices.
But in step-down converters it mostly works. With stepper motor drivers
that's a whole 'nother matter goose bumps, neck hair goes up.

C86 is a bit sub-optimal, should be between inductor and chip so it's
closer to pin 6. I assume GND is a full plane. If +VBAT is at least a
partial plane you could via pin 6 to it right near the pad, like you did
with pin 4. That change should be quite painless.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Hi Joerg,

"Joerg" wrote in message
. ..
Certainly doesn't look normal. Did you ever contact LTC about it?

No, but I suppose I should for the sake of completness here. As I've
mentioned, this isn't the first time I've seen a buck regulator behave like
this, and I'd love to nail down the cause and find a solution.

C86 is a bit sub-optimal, should be between inductor and chip so it's closer
to pin 6.

Good point.

I assume GND is a full plane.

Yes... the stack-up is...

Layer 1: Top - Routing
Layer 2: Full ground plane
Layer 3: Split plane, VBat in the area of the board shown, +3.3V (comes from a
linear regulator) over most of the board
Layer 4: Routing
Layer 5: Full plane, output of this regulator (1.2V)
Layer 6: Ground
Layer 7: Routing
Layer 8: Bottom - Routing

Thanks for your help,
---Joel

Joel Koltner wrote:
Hi Joerg,

"Joerg" wrote in message
. ..
Certainly doesn't look normal. Did you ever contact LTC about it?

No, but I suppose I should for the sake of completness here. As I've
mentioned, this isn't the first time I've seen a buck regulator behave like
this, and I'd love to nail down the cause and find a solution.


I have never seen one do that. But then again I rarely use PWM chips for
switchers. Have a hard time trusting them and their long term
availability ...

In the past there was more than one occasion where a chat with app
engineering at various mfgs ended up with them saying something like "Oh
drat!".


C86 is a bit sub-optimal, should be between inductor and chip so it's closer
to pin 6.

Good point.

I assume GND is a full plane.

Yes... the stack-up is...

Layer 1: Top - Routing
Layer 2: Full ground plane
Layer 3: Split plane, VBat in the area of the board shown, +3.3V (comes from a
linear regulator) over most of the board


Good, then you could place that via so the PWM chip has a much shorter
connection to VBAT. IIRC the trace was quite wide so you could probably
do that with a quick Gerber edit if your ECO procedure allows it.


Layer 4: Routing
Layer 5: Full plane, output of this regulator (1.2V)
Layer 6: Ground
Layer 7: Routing
Layer 8: Bottom - Routing

Thanks for your help,
---Joel




--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

On Wed, 30 Apr 2008 14:37:29 -0700, "Joel Koltner"
wrote:

For those of you who read the "slightly misbehaving switchers" thread (which
has long since scrolled off my news server), I've had the chance to take a
look at the behavior of the switcher in question now that it's on an 8-layer
board with a ground plane. I've attached the results in the same format as
the original document. The Reader's Digest version of the results seems to
be... "nothing much has changed" -- there's still noticeable jitter in the
duty cycle with input voltages around 3V.

In any case, since the original (2-layer PCB) ended up working OK, I'm not
particularly worried about this (even though I wish the jitter weren't there
and don't really understand what causes it), I just wanted to share the
results with everyone helped on with the original problem.

---Joel

I'm surprised that you got clean switching at all! That via carrying
all the high current spikes on pin 4 is modulating your feedback
voltage and compensation cap C84. C86 and C87 should have been
connected to pin 4 on the top layer with a copper pour. Plus, C87 and
L3 could have been placed more optimally to reduce the current loop
path. Switcher layout is critical if you want them to work cleanly.

I would have done the layout per the attached image.

---
Mark

Hi Mark,

"qrk" wrote in message
...
I'm surprised that you got clean switching at all! That via carrying
all the high current spikes on pin 4 is modulating your feedback
voltage and compensation cap C84.

That sounds plausible.

C86 and C87 should have been
connected to pin 4 on the top layer with a copper pour.

Yeah, I should have had the layout guy do that, in retrospect.

Plus, C87 and
L3 could have been placed more optimally to reduce the current loop
path.

It's not obvious from the layout in the PDF you're looking at, but there's a
big connector on the bottom of the PCB (centered roughly below C28/C3) that
probably dissuaded him from trying to move L3 and C87 closer... although with
some effort he still could have done it, I expect. I'm apparently not very
good at "nicely" asking people to do this sort of thing though... I'm told I
come off as confrontational ("Please change this to look like this."), and I
get annoyed that the layout guy seems to think these are unnecessary or
difficult changes.

I would have done the layout per the attached image.

Thanks, that's pretty nice. It's actually very similar to the two-layer
layout I had, if you saw that.

What's your PCB tool of choice there, if you don't mind my asking?

I sent this same file off to the local Linear Tech FAE and he's responded back
saying that he doesn't see any problems "yet" :-)... and could I send him some
data sheets? I have, so it'll be interesting to see what he says next.

---Joel

Joerg wrote:

In the past there was more than one occasion where a chat with app
engineering at various mfgs ended up with them saying something like "Oh
drat!".

The thing that bothers me about the scope capture of the
jitter is that it does not propagate throughout
the waveform, but only blurs one edge. That might mean
that the blur is the edge slope varying, not its timing. It
might be the switch switching at various speeds rather than
a various times. I want to see that jittery waveform
captured right at the top of the blurry negative going
swing, and blown up about 10 times wider. There is
something very strange going on there.

--
Regards,

John Popelish

On Thu, 1 May 2008 14:16:23 -0700, "Joel Koltner"
wrote:

Hi Mark,

"qrk" wrote in message
.. .
I'm surprised that you got clean switching at all! That via carrying
all the high current spikes on pin 4 is modulating your feedback
voltage and compensation cap C84.

That sounds plausible.

C86 and C87 should have been
connected to pin 4 on the top layer with a copper pour.

Yeah, I should have had the layout guy do that, in retrospect.

Plus, C87 and
L3 could have been placed more optimally to reduce the current loop
path.

It's not obvious from the layout in the PDF you're looking at, but there's a
big connector on the bottom of the PCB (centered roughly below C28/C3) that
probably dissuaded him from trying to move L3 and C87 closer... although with
some effort he still could have done it, I expect. I'm apparently not very
good at "nicely" asking people to do this sort of thing though... I'm told I
come off as confrontational ("Please change this to look like this."), and I
get annoyed that the layout guy seems to think these are unnecessary or
difficult changes.

Some layout folks tend to be artists and get annoyed when you suggest
something that isn't quite pretty. When I used to deal with layout
artists, I would put down an ultimatum and a sketch on how to do
critical areas. They would come back and show me something else that I
would "really like". Sometimes it took more effort to deal with them
than doing the board myself. Now days, I do all the PCB layout myself
since the layout is critical due to high-gain amplifiers, switching
power supplies, kW pulse amplifiers, and high-speed digital junk all
in close proximity.

I've had a colleague muck up the grounding on a similar switcher. It
was really unhappy due to poor ground connectivity practice.
Fortunately, a few jumper wires between critical ground points on the
power supply fixed it so he could get the rest of the board tested
out.

I would have done the layout per the attached image.

Thanks, that's pretty nice. It's actually very similar to the two-layer
layout I had, if you saw that.

What's your PCB tool of choice there, if you don't mind my asking?

I use Orcad Layout. I still use the old DOS Orcad schematic tools. The
Windows version is counterproductive.

I sent this same file off to the local Linear Tech FAE and he's responded back
saying that he doesn't see any problems "yet" :-)... and could I send him some
data sheets? I have, so it'll be interesting to see what he says next.

The FAE we have, Dave Green, is pretty good. I'm surprised your FAE
didn't catch the layout issues. This is something that LT stresses in
their data sheets. You can ask your FAE to send you the PCB layout
documentation for their evaluation board. It's quite helpful.

---
Mark