When using DAC/ADC pairs, which way is more resistant to noise and nonlinearities?
 

I am inexperienced with analog thingy.

My digital clock is 40MHz, modulates a 10mbps bit stream into some
waveforms.
The modulated output value lies between two narrow bands, 0-63 for input
zero
or 960-1023 for input ones, when input bit flips, output also change between
lower
band and higher band. When input bit remain unchanged, output flactuates
within
their narrow bands.

Now my task is to send this waveform through TI DAC290x-EVM (DAC chip) and
Analog AD9218 (ADC chip), and make the demodulator demodulate the ADC
outputs.

My digital outputs are in 2's compliment, I can easily convert that into
binary value (thus
between 448-576) if it's advantageous.

Which is better option?

When using DAC/ADC pairs, which way is more resistant to noise and nonlinearities?
 

"Frank" wrote in message
...
I am inexperienced with analog thingy.

My digital clock is 40MHz, modulates a 10mbps bit stream into some
waveforms.
The modulated output value lies between two narrow bands, 0-63 for input
zero
or 960-1023 for input ones, when input bit flips, output also change
between
lower
band and higher band. When input bit remain unchanged, output flactuates
within
their narrow bands.

Now my task is to send this waveform through TI DAC290x-EVM (DAC chip) and
Analog AD9218 (ADC chip), and make the demodulator demodulate the ADC
outputs.

My digital outputs are in 2's compliment, I can easily convert that into
binary value (thus
between 448-576) if it's advantageous.

Which is better option?








Does it make sense to shift the binary value left/right by 3 bits in my
digital chip?
It's likely to make it more resilient against gaussian noise in analog
domain.