For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

I think that would do it.

Thanks also to Lasse for the same suggestion.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

Do you want to build hardware, or just Spice this?

LT Spice has random signal generators. You could quantize one of them,
and drive a decoder.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On Wed, 01 Apr 2015 12:06:00 -0700, John Larkin
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

Do you want to build hardware, or just Spice this?

LT Spice has random signal generators. You could quantize one of them,
and drive a decoder.

"For a simulation situation..." ;-)

John F and Lasse have provided how to do it.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

I think that would do it.

Thanks also to Lasse for the same suggestion.

...Jim Thompson

I was puzzling over how to get 0000, but then it dawned... just use an
8-bit LFSR and use the last 4-bits.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

---
Yes.
---

I think that would do it.

---
OK :-)
---

Thanks also to Lasse for the same suggestion.

---
He posted earlier than I did, so the "win" is really his.

Also, perhaps not immediately apparent is that he also posted that
the length of the LFSR will determine the repeat of the one-hot
sequence out of the demux.

For example, if you use a maximal length 4 bit LFSR, the sequence
will repeat every 15 clocks, while if you use a maximal length 8 bit
LFSR the sequence will repeat every 255 clocks, and so on...

John Fields

On Wed, 01 Apr 2015 12:10:24 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 11:53:10 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 13:27:06 -0500, John Fields
wrote:

On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

---
If you use something like an HC154 with an LFSR driving its address
inputs to generate random one-hots on its outputs, will that work
for you?

John,

What are you saying... take the outputs of the LFSR broadside to drive
the address lines of the 'HC154?

I think that would do it.

Thanks also to Lasse for the same suggestion.

...Jim Thompson

I was puzzling over how to get 0000, but then it dawned... just use an
8-bit LFSR and use the last 4-bits.

...Jim Thompson

---
There's really nothing quite like that thrilling flash of discovery,
is there?

If you need 0000 out and you only want to use a 4 bit LFSR, then use
XNOR feedback to force the lockup state to 1111 instead of 0000 and
you'll magically jump over 1111 once per cycle.

If you need an LFSR with a maximal length of 2^n instead of 2^n-1,
then a pulse-stuffer is called for.

If there's any interest I'll post a schematic.

On Wed, 01 Apr 2015 12:08:34 -0700, Jim Thompson
wrote:

...snip...

"For a simulation situation..." ;-)

John F and Lasse have provided how to do it.

...Jim Thompson


For simulation I'd use the built-in rand() function of LTspice, if you
want gaussian instead of uniform distribution, use five rand()'s summed
appropriately. You said you like to use PSpice only, so create a text file
to use in a PWL type thingy THEN you can get completel control, likw
distribution and the elusive 1/f etc, any type statistics you want.

For Hardware to not have to go buy much, use the Soundcard and run it
directly with either a repeating pattern of random values, or from a
random number generator to get very long runs. The method of converting
FROM the audio output [BW is 10Hz to approx 100kHz] is left to the
'student'] The point here is that you can get repeatable random sequences
that are completely under your control.

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

On Wed, 01 Apr 2015 14:07:40 -0700, RobertMacy
wrote:

On Wed, 01 Apr 2015 12:08:34 -0700, Jim Thompson
wrote:

...snip...

"For a simulation situation..." ;-)

John F and Lasse have provided how to do it.

...Jim Thompson


For simulation I'd use the built-in rand() function of LTspice, if you
want gaussian instead of uniform distribution, use five rand()'s summed
appropriately. You said you like to use PSpice only, so create a text file
to use in a PWL type thingy THEN you can get completel control, likw
distribution and the elusive 1/f etc, any type statistics you want.

For Hardware to not have to go buy much, use the Soundcard and run it
directly with either a repeating pattern of random values, or from a
random number generator to get very long runs. The method of converting
FROM the audio output [BW is 10Hz to approx 100kHz] is left to the
'student'] The point here is that you can get repeatable random sequences
that are completely under your control.

I'm after "random" as in numbers 1-16, which will turn on specific I/Q
components of a modulation "constellation", such as 16-QAM... building
a carrier extractor with AGC and needed a stimulus ;-)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On 4/1/2015 6:31 PM, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state.... or you can just use a much larger LFSR so that the small bias
is in the noise. If you use a short sequence LFSR you may see the
artifacts in your signal anyway. Remember this is only pseudo-random.
Is 255 length sequence long enough for your needs?

--

Rick

On Thu, 02 Apr 2015 09:24:29 +1000, rickman wrote:

On 4/1/2015 6:31 PM, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16
outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of
those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154
demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may
cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state.... or you can just use a much larger LFSR so that the small bias
is in the noise. If you use a short sequence LFSR you may see the
artifacts in your signal anyway. Remember this is only pseudo-random.
Is 255 length sequence long enough for your needs?


longer lfsr would get my vote

On 2.4.15 01:31, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

...Jim Thompson


A longer LFSR is the simplest cure. 20 bits will give you a bias
of one per million.

Another possibility is to use a congruential generator, but it
needs quite a lot of arithmetic, one multiply and one add.

--

-Tauno Voipio

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

--
umop apisdn

On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.



--
umop apisdn

On Wed, 01 Apr 2015 12:14:13 -0700, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:
...snip....

How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

Uniform distribution sounds like a great 'first' test.

However, often modulators are not always set up to 'scramble' the data to
create uniform distribution. Does that mean you should also check some
weird distributions reflecting fixed/sloppy modulation? Especially if the
16 level space has any type of one to one relationship, like text, mime
format, or images which have repeating patterns [don't they?]

Anyway, just to be sure, you may want to try some weird distributions just
to make certain the AGC doesn't respond to these 'patterns'.

On Wed, 01 Apr 2015 15:31:25 -0700, Jim Thompson
wrote:

On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

...Jim Thompson
---
The cure is to force the counter into the all-zeros state (the
lockup state if you're using EXOR feedback) once per cycle and then
to force it back out again, like this:

https://www.dropbox.com/s/r7ea52axx6q6fny/LFSR.asc?dl=0

which'll give you a bias-free sequence since the counter will step
through all 256 states instead of just 255

John Fields

On 4/2/2015 6:48 AM, Jasen Betts wrote:
On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

You haven't seen the app note. Why can't it include the zero state with
modification?

--

Rick

On 2 Apr 2015 10:48:15 GMT, Jasen Betts wrote:

On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

---
That's not true, but I've heard that position defended on semantic
grounds because a "Linear Feedback Shift Register" can only include
EXOR feedback.

My position is that that's bogus, since by changing the name to
"Pseudo Random Sequence Generator" and employing the same additional
logic in the LFSR's feedback path, both circuits will be
topologically identical and each will visit all states.

John Fields

On 2015-04-02, rickman wrote:
On 4/2/2015 6:48 AM, Jasen Betts wrote:
On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

You haven't seen the app note. Why can't it include the zero state with
modification?

I think there's something about linear feedback that requires the
cycle length to be odd.


--
umop apisdn

On 2015-04-02, John Fields wrote:
On 2 Apr 2015 10:48:15 GMT, Jasen Betts wrote:

On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

---
That's not true, but I've heard that position defended on semantic
grounds because a "Linear Feedback Shift Register" can only include
EXOR feedback.

There is that: there are only three linear boolean operators, NOT,
XOR,XNOR, (and they can all be derived from XOR )

My position is that that's bogus, since by changing the name to
"Pseudo Random Sequence Generator" and employing the same additional
logic in the LFSR's feedback path, both circuits will be
topologically identical and each will visit all states.

That would make it a non-linear FSR

--
umop apisdn

On 4/2/2015 4:51 PM, Jasen Betts wrote:
On 2015-04-02, rickman wrote:
On 4/2/2015 6:48 AM, Jasen Betts wrote:
On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

You haven't seen the app note. Why can't it include the zero state with
modification?

I think there's something about linear feedback that requires the
cycle length to be odd.

The key word there is "something". Technically once you make this mod
it is not an LFSR anymore. But that is what the OP wants, something
that is *not* an LFSR because the LFSR only covers 2^N-1 states and he
wants 2^N.

A rose by any other name....

--

Rick

On 4/2/2015 4:51 PM, Jasen Betts wrote:
On 2015-04-02, rickman wrote:
On 4/2/2015 6:48 AM, Jasen Betts wrote:
On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

You haven't seen the app note. Why can't it include the zero state with
modification?

I think there's something about linear feedback that requires the
cycle length to be odd.


Maximum length sequences of even order are perfectly possible, but they
require more feedback taps.

Cheers

Phil Hobbs



--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

John Fields

On Thu, 02 Apr 2015 18:52:57 -0500, John Fields
wrote:

On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

John Fields

smirk:-}

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On 4/2/2015 7:52 PM, John Fields wrote:
On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that
would be four adders. I assume the modulo value is a typo and should be
65536 which comes free. I don't recall any 8 bit adder chips, so using
4 bit ones that would need chips 7 since when adding 64 * r, the lower 4
bits are always zero.

--

Rick

On 4/2/2015 8:25 PM, rickman wrote:
On 4/2/2015 7:52 PM, John Fields wrote:
On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that
would be four adders. I assume the modulo value is a typo and should be
65536 which comes free. I don't recall any 8 bit adder chips, so using
4 bit ones that would need chips 7 since when adding 64 * r, the lower 4
bits are always zero.

shl(6)
+----/----\ /--Just one chip on MS 4 bits
| \ L
| O-----\
| shl(3) / \
+----/----/ \
| \
r --+ O----\
| shl(1) / \
+----/----\ / \
| \ / O--- r'
| O-----/ /
| / /
+---------/ 74 ----/

Each 'O' is two 4 bit adders other than the one summing shf6 and shf3.
r is stored in an 8 bit register.

Maybe the modulo 65537 isn't a typo. With the addition of an even
number (74) the low order bit will never change unless the modulus is
odd. That's a whole different animal... But then the range is 0 to
65536, a 17 bit number. Anyone know the correct formula?

--

Rick

(On Fri, 03 Apr 2015 10:20:47 +1000, Jim Thompson
wrote:

On Thu, 02 Apr 2015 18:52:57 -0500, John Fields
wrote:

On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson
wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16
outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of
those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154
demux.
If you need better randomness, use four PRBSes of different
length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may
cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

John Fields

smirk:-}

...Jim Thompson

Better(?) / easier is a Linear congruence generator- the simplest is s =
5*s + 1 (then mod 16) this outputs the sequence:

0
1
6
15
12
13
2
11
8
9
14
7
4
5
10
3

(multiply by 5 is just a shift right by 2 bits and an addition) + another
addition of 1

mod 16 is just throw away everything but the 4 LSB's

I still think LFSR is better - mod 65537 would be a bitch

On 2015-04-03, rickman wrote:
On 4/2/2015 7:52 PM, John Fields wrote:
On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

it'd look A bit like a LFSR except with serial adders instead of XORS
and a bit tacked on to do the %65537

Given that task I'd take it as a hint to learn "FPGA"

Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that
would be four adders. I assume the modulo value is a typo and should be
65536 which comes free. I don't recall any 8 bit adder chips, so using
4 bit ones that would need chips 7 since when adding 64 * r, the lower 4
bits are always zero.

no, 65537 is correct.

mod 65537 isn't too hard, it'd need a second shift register to subtract the overflow
from the low 16 bits and subsequently add one if that substraction overflows.

this doesn't visit all 65537 states either: 65536 loops back on itself.
but it's not a desirable state.

I did this in Z80 assembler back in the 80s it took, 15 or so op codes
and used all of one register bank (7x 8bit), and I think about 50 clock
cycles, so that'd manage 12.5Khz.


--
umop apisdn

On 2 Apr 2015 20:59:32 GMT, Jasen Betts wrote:

On 2015-04-02, John Fields wrote:
On 2 Apr 2015 10:48:15 GMT, Jasen Betts wrote:

On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

---
That's not true, but I've heard that position defended on semantic
grounds because a "Linear Feedback Shift Register" can only include
EXOR feedback.

There is that: there are only three linear boolean operators, NOT,
XOR,XNOR, (and they can all be derived from XOR )

My position is that that's bogus, since by changing the name to
"Pseudo Random Sequence Generator" and employing the same additional
logic in the LFSR's feedback path, both circuits will be
topologically identical and each will visit all states.

That would make it a non-linear FSR

---
That's precisely why I choose to call them both PRSGs and allay the
semantic silliness in favor of what matters.

John Fields

On Thu, 02 Apr 2015 20:25:08 -0400, rickman
wrote:

On 4/2/2015 7:52 PM, John Fields wrote:
On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"
wrote:

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson
wrote:

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs
wrote:

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.

Cheers

Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

---
But, if you had to, what would it look like, schematic-wise?

Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that
would be four adders. I assume the modulo value is a typo and should be
65536 which comes free. I don't recall any 8 bit adder chips, so using
4 bit ones that would need chips 7 since when adding 64 * r, the lower 4
bits are always zero.

---
That's not a schematic, and there's many a slip 'twixt the cup and
the lip, especially when assumptions are made.

Can you post a real schematic showing what you're talking about,
please?

On Thu, 02 Apr 2015 17:42:55 -0400, rickman
wrote:

On 4/2/2015 4:51 PM, Jasen Betts wrote:
On 2015-04-02, rickman wrote:
On 4/2/2015 6:48 AM, Jasen Betts wrote:
On 2015-04-01, rickman wrote:
On 4/1/2015 6:31 PM, Jim Thompson wrote:

Do a search on the Xilinx web site for app notes on LFSR. Peter Alfke
published one which adds a few gates to specifically inject the zero
state....

yeah, but no LFSR visits all states.

You haven't seen the app note. Why can't it include the zero state with
modification?

I think there's something about linear feedback that requires the
cycle length to be odd.

The key word there is "something".

---
As noted earlier by Doctor Phil, there's _nothing_ that requires the
cycle length, maximal or otherwise, to be odd.
---

Technically once you make this mod it is not an LFSR anymore.

---
True; it reverts to being a Pseudo Random Sequence Generator, of
which an LFSR is a subset.
---

But that is what the OP wants, something that is *not* an LFSR
because the LFSR only covers 2^N-1 states and he wants 2^N.

---
Where did Jim say he was looking for 2^n?
---

A rose by any other name....

---
called a turd, by someone trusted, would stink.

On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


Jim do you have a model of a 7483?

On Tue, 14 Apr 2015 07:15:50 +1000, David Eather wrote:

On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


Jim do you have a model of a 7483?

or 74 x 283

On Tue, 14 Apr 2015 07:15:50 +1000, "David Eather"
wrote:

7483

Yep. A PSpice model. Unfortunately I think it will only run on
PSpice.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Tue, 14 Apr 2015 07:20:03 +1000, "David Eather"
wrote:

On Tue, 14 Apr 2015 07:15:50 +1000, David Eather wrote:

On Thu, 02 Apr 2015 04:00:25 +1000, Jim Thompson
wrote:

For a simulation situation I need a random number generator with a
twist...

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson


Jim do you have a model of a 7483?

or 74 x 283

Yes, also. I have a 16-long LFSR already running.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.