Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 07 Dec 2014 10:22:43 -0700, Jim Thompson
wrote:

Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Odd, clicking on URL, image didn't appear, just blank screen page.

On Sun, 07 Dec 2014 10:35:18 -0700, RobertMacy
wrote:

On Sun, 07 Dec 2014 10:22:43 -0700, Jim Thompson
wrote:

Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Odd, clicking on URL, image didn't appear, just blank screen page.

You're just lucky :-}

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On 7.12.14 19:22, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Kind of - an OR feeding a NAND and signal flow in reverse.
The standards require main signal flow from left to right
and top to bottom.

--

-TV

On 12/7/2014 10:22 AM, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

Depends on how *you* look at it. To me, it was immediately obvious
that the output is asserted (and that that assertion is HIGH) when
either the dogleg input at the left is LOW *or* both inputs at the
right are LOW.

The drawing suggests that NOR gates (the rightmost "AND") and NAND
gates (the leftmost "OR") are being used. One would typically
avoid "OR" gates -- which you would need if you elided the inverter
in the drawing and moved it to the dogleg input, instead.

[If you were drawing it *functionally*, the inverter would fold into
the output of the "AND" on the right (i.e., it would have bubbles on
input and output) turning it into an "OR" gate (positive logic).
The fact that this wasn't done, suggests it represents an actual
implementation instead of a functional description.]

On Sun, 07 Dec 2014 19:59:52 +0200, Tauno Voipio
wrote:

On 7.12.14 19:22, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Kind of - an OR feeding a NAND and signal flow in reverse.
The standards require main signal flow from left to right
and top to bottom.

But it did jog my memory of _long_ago_ teaching this stuff...

"Break the line, change the sign" ;-)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 07 Dec 2014 11:14:16 -0700, Don Y wrote:

On 12/7/2014 10:22 AM, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

Depends on how *you* look at it. To me, it was immediately obvious
that the output is asserted (and that that assertion is HIGH) when
either the dogleg input at the left is LOW *or* both inputs at the
right are LOW.

The drawing suggests that NOR gates (the rightmost "AND") and NAND
gates (the leftmost "OR") are being used. One would typically
avoid "OR" gates -- which you would need if you elided the inverter
in the drawing and moved it to the dogleg input, instead.

[If you were drawing it *functionally*, the inverter would fold into
the output of the "AND" on the right (i.e., it would have bubbles on
input and output) turning it into an "OR" gate (positive logic).
The fact that this wasn't done, suggests it represents an actual
implementation instead of a functional description.]

Structurally, at least in CMOS, there's only a minute area penalty for
NOR versus NAND... hardly enough to write home about... in the NOR two
wells are required for the PMOS, but in the NAND you're stacking NMOS
which requires they each be larger than in the NOR... particularly if
you're a stickler for symmetry, as I am ;-)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 07 Dec 2014 11:25:34 -0700, Jim Thompson
wrote:

On Sun, 07 Dec 2014 11:14:16 -0700, Don Y wrote:

On 12/7/2014 10:22 AM, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

Depends on how *you* look at it. To me, it was immediately obvious
that the output is asserted (and that that assertion is HIGH) when
either the dogleg input at the left is LOW *or* both inputs at the
right are LOW.

The drawing suggests that NOR gates (the rightmost "AND") and NAND
gates (the leftmost "OR") are being used. One would typically
avoid "OR" gates -- which you would need if you elided the inverter
in the drawing and moved it to the dogleg input, instead.

[If you were drawing it *functionally*, the inverter would fold into
the output of the "AND" on the right (i.e., it would have bubbles on
input and output) turning it into an "OR" gate (positive logic).
The fact that this wasn't done, suggests it represents an actual
implementation instead of a functional description.]

Structurally, at least in CMOS, there's only a minute area penalty for
NOR versus NAND... hardly enough to write home about... in the NOR two
wells are required for the PMOS, but in the NAND you're stacking NMOS
which requires they each be larger than in the NOR... particularly if
you're a stickler for symmetry, as I am ;-)

...Jim Thompson

For instance, here is a 3-input NAND...

http://www.analog-innovations.com/SED/3-IN-NAND.pdf

Inputs A, B, C exhibit the same thresholds AND delays to output.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

In message , Jim Thompson
writes
On Sun, 07 Dec 2014 19:59:52 +0200, Tauno Voipio
wrote:

On 7.12.14 19:22, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Kind of - an OR feeding a NAND and signal flow in reverse.
The standards require main signal flow from left to right
and top to bottom.

But it did jog my memory of _long_ago_ teaching this stuff...

"Break the line, change the sign" ;-)

...Jim Thompson

I'd have to draw a Karnaugh Map - whatever those are.

Brian

--
Brian Howie

On 12/7/2014 11:25 AM, Jim Thompson wrote:
On Sun, 07 Dec 2014 11:14:16 -0700, Don Y wrote:

On 12/7/2014 10:22 AM, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

Depends on how *you* look at it. To me, it was immediately obvious
that the output is asserted (and that that assertion is HIGH) when
either the dogleg input at the left is LOW *or* both inputs at the
right are LOW.

The drawing suggests that NOR gates (the rightmost "AND") and NAND
gates (the leftmost "OR") are being used. One would typically
avoid "OR" gates -- which you would need if you elided the inverter
in the drawing and moved it to the dogleg input, instead.

[If you were drawing it *functionally*, the inverter would fold into
the output of the "AND" on the right (i.e., it would have bubbles on
input and output) turning it into an "OR" gate (positive logic).
The fact that this wasn't done, suggests it represents an actual
implementation instead of a functional description.]

Structurally, at least in CMOS, there's only a minute area penalty for
NOR versus NAND... hardly enough to write home about... in the NOR two
wells are required for the PMOS, but in the NAND you're stacking NMOS
which requires they each be larger than in the NOR... particularly if
you're a stickler for symmetry, as I am ;-)

Presumably, there are no inverters "off to the right" (or left) of your
drawing. So, the way it was drawn is the most economical way of
*expressing* that functionality while mimicking the implementation.

They could have, instead, replaced the NOR at the right with a pair of
inverters (bubbled inputs to reflect the LOW level of the off-page signals
that is significant to the function) feeding a NAND *without* a following
inverter. But this would, IMO, be less intuitive to someone trying to
understand what was being *done*, here.

[If not reflecting the implementation, I'd have removed the inverter AND
and added a bubble on the output of the NOR at the right -- IMO, this
makes it much clearer (but, lots of folks seem to like thinking in
positive logic with 'real' devices instead of functionally). Of course,
signal names make things a bit easier to understand...]

On Sun, 7 Dec 2014 19:32:33 +0000, Brian Howie
wrote:

In message , Jim Thompson
writes
On Sun, 07 Dec 2014 19:59:52 +0200, Tauno Voipio
wrote:

On 7.12.14 19:22, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Kind of - an OR feeding a NAND and signal flow in reverse.
The standards require main signal flow from left to right
and top to bottom.

But it did jog my memory of _long_ago_ teaching this stuff...

"Break the line, change the sign" ;-)

...Jim Thompson

I'd have to draw a Karnaugh Map - whatever those are.

Brian


http://www.csus.edu/indiv/p/pangj/class/cpe64/ademo/L1_Demo_Demorgan.pdf

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On Sun, 07 Dec 2014 12:38:13 -0700, Don Y wrote:

On 12/7/2014 11:25 AM, Jim Thompson wrote:
On Sun, 07 Dec 2014 11:14:16 -0700, Don Y wrote:

On 12/7/2014 10:22 AM, Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

Depends on how *you* look at it. To me, it was immediately obvious
that the output is asserted (and that that assertion is HIGH) when
either the dogleg input at the left is LOW *or* both inputs at the
right are LOW.

The drawing suggests that NOR gates (the rightmost "AND") and NAND
gates (the leftmost "OR") are being used. One would typically
avoid "OR" gates -- which you would need if you elided the inverter
in the drawing and moved it to the dogleg input, instead.

[If you were drawing it *functionally*, the inverter would fold into
the output of the "AND" on the right (i.e., it would have bubbles on
input and output) turning it into an "OR" gate (positive logic).
The fact that this wasn't done, suggests it represents an actual
implementation instead of a functional description.]

Structurally, at least in CMOS, there's only a minute area penalty for
NOR versus NAND... hardly enough to write home about... in the NOR two
wells are required for the PMOS, but in the NAND you're stacking NMOS
which requires they each be larger than in the NOR... particularly if
you're a stickler for symmetry, as I am ;-)

Presumably, there are no inverters "off to the right" (or left) of your
drawing. So, the way it was drawn is the most economical way of
*expressing* that functionality while mimicking the implementation.

They could have, instead, replaced the NOR at the right with a pair of
inverters (bubbled inputs to reflect the LOW level of the off-page signals
that is significant to the function) feeding a NAND *without* a following
inverter. But this would, IMO, be less intuitive to someone trying to
understand what was being *done*, here.

[If not reflecting the implementation, I'd have removed the inverter AND
and added a bubble on the output of the NOR at the right -- IMO, this
makes it much clearer (but, lots of folks seem to like thinking in
positive logic with 'real' devices instead of functionally). Of course,
signal names make things a bit easier to understand...]

Yep. I initially had a WTF moment, then it all came back to me ;-)

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

RobertMacy wrote:
On Sun, 07 Dec 2014 10:22:43 -0700, Jim Thompson
wrote:

Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson


Odd, clicking on URL, image didn't appear, just blank screen page.
Saw same thing, but noticed "magnifying" glass with "-"; use that.
Read schematic sdrawkcab.

In article , To-Email-Use-
says...
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson

Invert the inputs invert the output and replace the AND with OR or vice
versa... Is that where you are going?

In article , To-Email-Use-
says...
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

...Jim Thompson

Maybe they just wanted to be more descriptive what the actual hardware
inside the IC is, not just the functionality?

Jim Thompson wrote:
Is this an attempt to obfuscate...

http://www.analog-innovations.com/SED/DataSheetAnnoyance.png

figuring that everyone is a dummy and doesn't know De Morgan's
theorems?

It looks like they were trying to use the mixed-logic notation
championed by the otherwise excellent "The Art of Digital Design" by
Winkel and Prosser.


--
Reply in group, but if emailing add one more
zero, and remove the last word.