Above is the schematic for an audio amp I am hoping to build for one side of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1% for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would have
used .01% for the 2.7K also, but my candy store was out of them. May have
to order some...

Anyway, am hoping to get some feedback on the design, as I am NOT an EE, and
really have no idea as to what I am attempting here (if that isn't already
obvious.) If anyone sees anything particularly stupid, I am hoping they
will say something so I can troubleshoot it at this point, rather than on
the perfboard. Comments are sought, good, bad or indifferent. Blast away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for this
biasing network, I will happily upload them. Otherwise, I'll try to shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...

On Wed, 11 Jan 2012 08:53:29 -0600, "Dave" wrote:



Above is the schematic for an audio amp I am hoping to build for one side of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1% for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would have
used .01% for the 2.7K also, but my candy store was out of them. May have
to order some...

Jfets characteristics are all over the place; 4:1 or even 10:1 on
Idsss between parts is common. 5% resistors are plenty good enough.



Anyway, am hoping to get some feedback on the design, as I am NOT an EE, and
really have no idea as to what I am attempting here (if that isn't already
obvious.) If anyone sees anything particularly stupid, I am hoping they
will say something so I can troubleshoot it at this point, rather than on
the perfboard. Comments are sought, good, bad or indifferent. Blast away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for this
biasing network, I will happily upload them. Otherwise, I'll try to shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...


May I suggest that you spread out the schematic and generally clean it
up a bit? It's hard to read, and there are a number of intersections
that might or might not be connections.

The caps all look small in value.

John

"John Larkin" wrote in message
...
On Wed, 11 Jan 2012 08:53:29 -0600, "Dave" wrote:



Above is the schematic for an audio amp I am hoping to build for one side
of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1% for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would have
used .01% for the 2.7K also, but my candy store was out of them. May have
to order some...

Jfets characteristics are all over the place; 4:1 or even 10:1 on
Idsss between parts is common. 5% resistors are plenty good enough.

\

Hmm. I understand this to be the case, but my NTE JFETS seem to contradict
the idea. Still, I am planning on taking measurements in the actual circuit
to make sure I am on target. Thanks.



Anyway, am hoping to get some feedback on the design, as I am NOT an EE,
and
really have no idea as to what I am attempting here (if that isn't already
obvious.) If anyone sees anything particularly stupid, I am hoping they
will say something so I can troubleshoot it at this point, rather than on
the perfboard. Comments are sought, good, bad or indifferent. Blast
away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for this
biasing network, I will happily upload them. Otherwise, I'll try to shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...


May I suggest that you spread out the schematic and generally clean it
up a bit? It's hard to read, and there are a number of intersections
that might or might not be connections.

The caps all look small in value.

John


Yeah, it is rather cramped. Apologies. Will work on that, for the sake of
clarity. Thanks again.

Dave

Oh, and all the caps (I *think*) are .1uF ceramic disks. This is small in
value? I'm not sure I understand...

"Dave" wrote in message
ica...

"John Larkin" wrote in
message ...
On Wed, 11 Jan 2012 08:53:29 -0600, "Dave" wrote:



Above is the schematic for an audio amp I am hoping to build for one side
of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1%
for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would have
used .01% for the 2.7K also, but my candy store was out of them. May
have
to order some...

Jfets characteristics are all over the place; 4:1 or even 10:1 on
Idsss between parts is common. 5% resistors are plenty good enough.

\

Hmm. I understand this to be the case, but my NTE JFETS seem to
contradict the idea. Still, I am planning on taking measurements in the
actual circuit to make sure I am on target. Thanks.



Anyway, am hoping to get some feedback on the design, as I am NOT an EE,
and
really have no idea as to what I am attempting here (if that isn't
already
obvious.) If anyone sees anything particularly stupid, I am hoping they
will say something so I can troubleshoot it at this point, rather than on
the perfboard. Comments are sought, good, bad or indifferent. Blast
away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end
of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for
this
biasing network, I will happily upload them. Otherwise, I'll try to shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...


May I suggest that you spread out the schematic and generally clean it
up a bit? It's hard to read, and there are a number of intersections
that might or might not be connections.

The caps all look small in value.

John


Yeah, it is rather cramped. Apologies. Will work on that, for the sake
of clarity. Thanks again.

Dave

Oh, and all the caps (I *think*) are .1uF ceramic disks. This is small in
value? I'm not sure I understand...



Or, do you mean that the *resistor* values seem small? That I could
see, as they might appear such. If I'm wrong than I'm wrong, but these are
the numbers I come up with as optimum for different reasons.

Thanks.

Dave

Assuming everything about the circuit is as usually intended (a series of
common-emitter stages, or common-source for the JFET), you are missing two
interstage coupling capacitors. You indicate several bias resistor
dividers (R2/R1, R3/R4), but these are affected by the voltages that the
preceeding stage produces (from R12/J1 or R10/Q1).

The common-side bypass capacitors C1, C2 and C3 are working against the
output impedance of the transistors, which are approximately 1/Gm ohms for
the JFET, and around (0.025V / Ic) ohms for the BJTs. This is
significantly lower than the associated bias resistors, because
transistors are active devices. Typically the impedance is under 100
ohms; under real conditions, the 2N5486 might be closer to 300 ohms, while
the BJTs might be 10 ohms or less. A 0.1uF capacitor will then have a
cutoff frequency of F = 1 / (2*pi*R*C) = 15.9kHz, which is very high -- in
fact, so high that, for much of the audio range, the circuit will behave
as if they are not there. In that case, the large value emitter resistors
reduce gain significantly from the high frequency case. You'll notice
this as a peak in high-frequency gain above a few kHz, causing it to sound
very tinny or screeching.

Because the impedances are typically on the order of kohms or less,
transistor circuits like this often use coupling capacitors of several uF,
and bypass capacitors up to 100uF (more for power stages of this type).
Capacitors in this range are usually electrolytic, so be careful to assign
the '+' side to the higher voltage side (usually the collector/drain side,
but check to be sure).

Strictly speaking, coupling capacitors are not required for this type of
circuit, but only if you have global feedback setting an equilibrium
condition. Trying to adjust the setpoint of the whole chain with a couple
resistors at the front is doomed to failure.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

"Dave" wrote in message
ica...

"John Larkin" wrote in
message ...
On Wed, 11 Jan 2012 08:53:29 -0600, "Dave" wrote:



Above is the schematic for an audio amp I am hoping to build for one
side of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1%
for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would
have
used .01% for the 2.7K also, but my candy store was out of them. May
have
to order some...

Jfets characteristics are all over the place; 4:1 or even 10:1 on
Idsss between parts is common. 5% resistors are plenty good enough.

\

Hmm. I understand this to be the case, but my NTE JFETS seem to
contradict the idea. Still, I am planning on taking measurements in the
actual circuit to make sure I am on target. Thanks.



Anyway, am hoping to get some feedback on the design, as I am NOT an
EE, and
really have no idea as to what I am attempting here (if that isn't
already
obvious.) If anyone sees anything particularly stupid, I am hoping
they
will say something so I can troubleshoot it at this point, rather than
on
the perfboard. Comments are sought, good, bad or indifferent. Blast
away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end
of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for
this
biasing network, I will happily upload them. Otherwise, I'll try to
shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...


May I suggest that you spread out the schematic and generally clean it
up a bit? It's hard to read, and there are a number of intersections
that might or might not be connections.

The caps all look small in value.

John


Yeah, it is rather cramped. Apologies. Will work on that, for the sake
of clarity. Thanks again.

Dave

Oh, and all the caps (I *think*) are .1uF ceramic disks. This is small
in value? I'm not sure I understand...

My God, thank you, Tim. I now have something to work with and for. Can
hardly believe I left out the interstage coupling capacitors, but that's
what I did. Like I said, I am no EE, but I am trying to learn. I will
weigh the information in your post so carefully... Much appreciated.

Dave


"Tim Williams" wrote in message
...
Assuming everything about the circuit is as usually intended (a series of
common-emitter stages, or common-source for the JFET), you are missing two
interstage coupling capacitors. You indicate several bias resistor
dividers (R2/R1, R3/R4), but these are affected by the voltages that the
preceeding stage produces (from R12/J1 or R10/Q1).

The common-side bypass capacitors C1, C2 and C3 are working against the
output impedance of the transistors, which are approximately 1/Gm ohms for
the JFET, and around (0.025V / Ic) ohms for the BJTs. This is
significantly lower than the associated bias resistors, because
transistors are active devices. Typically the impedance is under 100
ohms; under real conditions, the 2N5486 might be closer to 300 ohms, while
the BJTs might be 10 ohms or less. A 0.1uF capacitor will then have a
cutoff frequency of F = 1 / (2*pi*R*C) = 15.9kHz, which is very high -- in
fact, so high that, for much of the audio range, the circuit will behave
as if they are not there. In that case, the large value emitter resistors
reduce gain significantly from the high frequency case. You'll notice
this as a peak in high-frequency gain above a few kHz, causing it to sound
very tinny or screeching.

Because the impedances are typically on the order of kohms or less,
transistor circuits like this often use coupling capacitors of several uF,
and bypass capacitors up to 100uF (more for power stages of this type).
Capacitors in this range are usually electrolytic, so be careful to assign
the '+' side to the higher voltage side (usually the collector/drain side,
but check to be sure).

Strictly speaking, coupling capacitors are not required for this type of
circuit, but only if you have global feedback setting an equilibrium
condition. Trying to adjust the setpoint of the whole chain with a couple
resistors at the front is doomed to failure.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

"Dave" wrote in message
ica...

"John Larkin" wrote in
message ...
On Wed, 11 Jan 2012 08:53:29 -0600, "Dave" wrote:



Above is the schematic for an audio amp I am hoping to build for one
side of
an intercom for my front door. I am using a 7812 to provide +12V, and
precision resistors (1% for the 2.7K and .01% for the 4K as well as 1%
for
the 4.02K, which actually measures 4.02K) to bias the JFET. I would
have
used .01% for the 2.7K also, but my candy store was out of them. May
have
to order some...

Jfets characteristics are all over the place; 4:1 or even 10:1 on
Idsss between parts is common. 5% resistors are plenty good enough.

\

Hmm. I understand this to be the case, but my NTE JFETS seem to
contradict the idea. Still, I am planning on taking measurements in the
actual circuit to make sure I am on target. Thanks.



Anyway, am hoping to get some feedback on the design, as I am NOT an EE,
and
really have no idea as to what I am attempting here (if that isn't
already
obvious.) If anyone sees anything particularly stupid, I am hoping they
will say something so I can troubleshoot it at this point, rather than
on
the perfboard. Comments are sought, good, bad or indifferent. Blast
away.
I have a lot to learn, and would like to get started. Many thanks.

Dave

PS: just for the record, input is open end of C5 and output is open end
of
C4. The JFET's IDSS is 3mA, and if anyone wants to see the calcs for
this
biasing network, I will happily upload them. Otherwise, I'll try to
shut
up. Again, my thanks. Hoping I haven't already committed some mortal
sin...


May I suggest that you spread out the schematic and generally clean it
up a bit? It's hard to read, and there are a number of intersections
that might or might not be connections.

The caps all look small in value.

John


Yeah, it is rather cramped. Apologies. Will work on that, for the sake
of clarity. Thanks again.

Dave

Oh, and all the caps (I *think*) are .1uF ceramic disks. This is small
in value? I'm not sure I understand...

Thoughts and suggestions are again welcome and sought.

Thanks,

Dave

On Fri, 13 Jan 2012 11:00:18 -0600, "Dave" wrote:



Thoughts and suggestions are again welcome and sought.

Thanks,

Dave

---
Version 4
SHEET 1 932 680
WIRE -16 16 -256 16
WIRE 96 16 -16 16
WIRE 272 16 96 16
WIRE 368 16 272 16
WIRE 544 16 368 16
WIRE 640 16 544 16
WIRE -16 64 -16 16
WIRE 96 64 96 16
WIRE 272 64 272 16
WIRE 368 64 368 16
WIRE 544 64 544 16
WIRE 640 64 640 16
WIRE 96 192 96 144
WIRE 144 192 96 192
WIRE 272 192 272 144
WIRE 272 192 208 192
WIRE 368 192 368 144
WIRE 416 192 368 192
WIRE 544 192 544 144
WIRE 544 192 480 192
WIRE 640 192 640 144
WIRE 720 192 640 192
WIRE 848 192 784 192
WIRE 368 208 368 192
WIRE 640 208 640 192
WIRE 96 240 96 192
WIRE 272 256 272 192
WIRE 304 256 272 256
WIRE 544 256 544 192
WIRE 576 256 544 256
WIRE -112 288 -144 288
WIRE -16 288 -16 144
WIRE -16 288 -48 288
WIRE 848 288 848 192
WIRE -16 304 -16 288
WIRE 48 304 -16 304
WIRE 176 336 96 336
WIRE 368 336 368 304
WIRE 448 336 368 336
WIRE 640 336 640 304
WIRE 736 336 640 336
WIRE -16 352 -16 304
WIRE 96 352 96 336
WIRE 272 352 272 256
WIRE 368 352 368 336
WIRE 544 352 544 256
WIRE 640 352 640 336
WIRE -256 368 -256 16
WIRE -144 368 -144 288
WIRE 176 368 176 336
WIRE 448 368 448 336
WIRE 736 368 736 336
WIRE -256 480 -256 448
WIRE -144 480 -144 448
WIRE -144 480 -256 480
WIRE -16 480 -16 432
WIRE -16 480 -144 480
WIRE 96 480 96 432
WIRE 96 480 -16 480
WIRE 176 480 176 432
WIRE 176 480 96 480
WIRE 272 480 272 432
WIRE 272 480 176 480
WIRE 368 480 368 432
WIRE 368 480 272 480
WIRE 448 480 448 432
WIRE 448 480 368 480
WIRE 544 480 544 432
WIRE 544 480 448 480
WIRE 640 480 640 432
WIRE 640 480 544 480
WIRE 736 480 736 432
WIRE 736 480 640 480
WIRE 848 480 848 368
WIRE 848 480 736 480
WIRE -256 544 -256 480
FLAG -256 544 0
SYMBOL res 80 48 R0
SYMATTR InstName R2
SYMATTR Value 820
SYMBOL res 256 48 R0
SYMATTR InstName R3
SYMATTR Value 80K
SYMBOL res 352 48 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 528 48 R0
SYMATTR InstName R5
SYMATTR Value 5.1K
SYMBOL res 624 48 R0
SYMATTR InstName R6
SYMATTR Value 510
SYMBOL res -32 48 R0
SYMATTR InstName R1
SYMATTR Value 2.7K
SYMBOL njf 48 240 R0
WINDOW 3 54 60 Left 2
SYMATTR InstName J1
SYMATTR Value 2N5486
SYMBOL res 80 336 R0
WINDOW 0 35 59 Left 2
WINDOW 3 22 90 Left 2
SYMATTR InstName R8
SYMATTR Value 4.02K
SYMBOL res -32 336 R0
SYMATTR InstName R7
SYMATTR Value 4K
SYMBOL cap -48 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100µ
SYMBOL cap 160 368 R0
SYMATTR InstName C3
SYMATTR Value 4.7µ
SYMBOL cap 208 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100µ
SYMBOL npn 304 208 R0
SYMATTR InstName Q1
SYMATTR Value 2N5210
SYMBOL res 352 336 R0
SYMATTR InstName R10
SYMATTR Value 2K
SYMBOL cap 432 368 R0
SYMATTR InstName C5
SYMATTR Value 4.7µ
SYMBOL res 256 336 R0
SYMATTR InstName R9
SYMATTR Value 39K
SYMBOL npn 576 208 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 624 336 R0
SYMATTR InstName R12
SYMATTR Value 470
SYMBOL cap 720 368 R0
SYMATTR InstName C6
SYMATTR Value 4.7µ
SYMBOL cap 480 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100µ
SYMBOL res 528 336 R0
SYMATTR InstName R11
SYMATTR Value 4.7K
SYMBOL cap 784 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 100µ
SYMBOL voltage -144 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 .01 1000)
SYMATTR Value2 AC 1
SYMBOL res 832 272 R0
SYMATTR InstName R13
SYMATTR Value 1000
SYMBOL voltage -256 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12
TEXT 38 520 Left 2 !;tran .01
TEXT -232 520 Left 2 !.ac oct 1024 10 100000

--
JF

"John Fields" wrote in message
...
On Fri, 13 Jan 2012 11:00:18 -0600, "Dave" wrote:



Thoughts and suggestions are again welcome and sought.

Thanks,

Dave

---
Version 4
SHEET 1 932 680
WIRE -16 16 -256 16
WIRE 96 16 -16 16
WIRE 272 16 96 16
WIRE 368 16 272 16
WIRE 544 16 368 16
WIRE 640 16 544 16
WIRE -16 64 -16 16
WIRE 96 64 96 16
WIRE 272 64 272 16
WIRE 368 64 368 16
WIRE 544 64 544 16
WIRE 640 64 640 16
WIRE 96 192 96 144
WIRE 144 192 96 192
WIRE 272 192 272 144
WIRE 272 192 208 192
WIRE 368 192 368 144
WIRE 416 192 368 192
WIRE 544 192 544 144
WIRE 544 192 480 192
WIRE 640 192 640 144
WIRE 720 192 640 192
WIRE 848 192 784 192
WIRE 368 208 368 192
WIRE 640 208 640 192
WIRE 96 240 96 192
WIRE 272 256 272 192
WIRE 304 256 272 256
WIRE 544 256 544 192
WIRE 576 256 544 256
WIRE -112 288 -144 288
WIRE -16 288 -16 144
WIRE -16 288 -48 288
WIRE 848 288 848 192
WIRE -16 304 -16 288
WIRE 48 304 -16 304
WIRE 176 336 96 336
WIRE 368 336 368 304
WIRE 448 336 368 336
WIRE 640 336 640 304
WIRE 736 336 640 336
WIRE -16 352 -16 304
WIRE 96 352 96 336
WIRE 272 352 272 256
WIRE 368 352 368 336
WIRE 544 352 544 256
WIRE 640 352 640 336
WIRE -256 368 -256 16
WIRE -144 368 -144 288
WIRE 176 368 176 336
WIRE 448 368 448 336
WIRE 736 368 736 336
WIRE -256 480 -256 448
WIRE -144 480 -144 448
WIRE -144 480 -256 480
WIRE -16 480 -16 432
WIRE -16 480 -144 480
WIRE 96 480 96 432
WIRE 96 480 -16 480
WIRE 176 480 176 432
WIRE 176 480 96 480
WIRE 272 480 272 432
WIRE 272 480 176 480
WIRE 368 480 368 432
WIRE 368 480 272 480
WIRE 448 480 448 432
WIRE 448 480 368 480
WIRE 544 480 544 432
WIRE 544 480 448 480
WIRE 640 480 640 432
WIRE 640 480 544 480
WIRE 736 480 736 432
WIRE 736 480 640 480
WIRE 848 480 848 368
WIRE 848 480 736 480
WIRE -256 544 -256 480
FLAG -256 544 0
SYMBOL res 80 48 R0
SYMATTR InstName R2
SYMATTR Value 820
SYMBOL res 256 48 R0
SYMATTR InstName R3
SYMATTR Value 80K
SYMBOL res 352 48 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 528 48 R0
SYMATTR InstName R5
SYMATTR Value 5.1K
SYMBOL res 624 48 R0
SYMATTR InstName R6
SYMATTR Value 510
SYMBOL res -32 48 R0
SYMATTR InstName R1
SYMATTR Value 2.7K
SYMBOL njf 48 240 R0
WINDOW 3 54 60 Left 2
SYMATTR InstName J1
SYMATTR Value 2N5486
SYMBOL res 80 336 R0
WINDOW 0 35 59 Left 2
WINDOW 3 22 90 Left 2
SYMATTR InstName R8
SYMATTR Value 4.02K
SYMBOL res -32 336 R0
SYMATTR InstName R7
SYMATTR Value 4K
SYMBOL cap -48 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100µ
SYMBOL cap 160 368 R0
SYMATTR InstName C3
SYMATTR Value 4.7µ
SYMBOL cap 208 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100µ
SYMBOL npn 304 208 R0
SYMATTR InstName Q1
SYMATTR Value 2N5210
SYMBOL res 352 336 R0
SYMATTR InstName R10
SYMATTR Value 2K
SYMBOL cap 432 368 R0
SYMATTR InstName C5
SYMATTR Value 4.7µ
SYMBOL res 256 336 R0
SYMATTR InstName R9
SYMATTR Value 39K
SYMBOL npn 576 208 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 624 336 R0
SYMATTR InstName R12
SYMATTR Value 470
SYMBOL cap 720 368 R0
SYMATTR InstName C6
SYMATTR Value 4.7µ
SYMBOL cap 480 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100µ
SYMBOL res 528 336 R0
SYMATTR InstName R11
SYMATTR Value 4.7K
SYMBOL cap 784 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 100µ
SYMBOL voltage -144 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 .01 1000)
SYMATTR Value2 AC 1
SYMBOL res 832 272 R0
SYMATTR InstName R13
SYMATTR Value 1000
SYMBOL voltage -256 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12
TEXT 38 520 Left 2 !;tran .01
TEXT -232 520 Left 2 !.ac oct 1024 10 100000

--
JF

Hello John, and thank you for this info. Unfortunately I can'tremember waht
to do with a netlist for LTSpice. Could you possibly spare a word or two,
and clue me in? I've only done this once before, I think, and the memory o
what I did eludes me.

Thanks,

Dave

On Sat, 14 Jan 2012 19:32:42 -0600, "Dave" wrote:


"John Fields" wrote in message
.. .
On Fri, 13 Jan 2012 11:00:18 -0600, "Dave" wrote:



Thoughts and suggestions are again welcome and sought.

Thanks,

Dave

---
Version 4
SHEET 1 932 680
WIRE -16 16 -256 16
WIRE 96 16 -16 16
WIRE 272 16 96 16
WIRE 368 16 272 16
WIRE 544 16 368 16
WIRE 640 16 544 16
WIRE -16 64 -16 16
WIRE 96 64 96 16
WIRE 272 64 272 16
WIRE 368 64 368 16
WIRE 544 64 544 16
WIRE 640 64 640 16
WIRE 96 192 96 144
WIRE 144 192 96 192
WIRE 272 192 272 144
WIRE 272 192 208 192
WIRE 368 192 368 144
WIRE 416 192 368 192
WIRE 544 192 544 144
WIRE 544 192 480 192
WIRE 640 192 640 144
WIRE 720 192 640 192
WIRE 848 192 784 192
WIRE 368 208 368 192
WIRE 640 208 640 192
WIRE 96 240 96 192
WIRE 272 256 272 192
WIRE 304 256 272 256
WIRE 544 256 544 192
WIRE 576 256 544 256
WIRE -112 288 -144 288
WIRE -16 288 -16 144
WIRE -16 288 -48 288
WIRE 848 288 848 192
WIRE -16 304 -16 288
WIRE 48 304 -16 304
WIRE 176 336 96 336
WIRE 368 336 368 304
WIRE 448 336 368 336
WIRE 640 336 640 304
WIRE 736 336 640 336
WIRE -16 352 -16 304
WIRE 96 352 96 336
WIRE 272 352 272 256
WIRE 368 352 368 336
WIRE 544 352 544 256
WIRE 640 352 640 336
WIRE -256 368 -256 16
WIRE -144 368 -144 288
WIRE 176 368 176 336
WIRE 448 368 448 336
WIRE 736 368 736 336
WIRE -256 480 -256 448
WIRE -144 480 -144 448
WIRE -144 480 -256 480
WIRE -16 480 -16 432
WIRE -16 480 -144 480
WIRE 96 480 96 432
WIRE 96 480 -16 480
WIRE 176 480 176 432
WIRE 176 480 96 480
WIRE 272 480 272 432
WIRE 272 480 176 480
WIRE 368 480 368 432
WIRE 368 480 272 480
WIRE 448 480 448 432
WIRE 448 480 368 480
WIRE 544 480 544 432
WIRE 544 480 448 480
WIRE 640 480 640 432
WIRE 640 480 544 480
WIRE 736 480 736 432
WIRE 736 480 640 480
WIRE 848 480 848 368
WIRE 848 480 736 480
WIRE -256 544 -256 480
FLAG -256 544 0
SYMBOL res 80 48 R0
SYMATTR InstName R2
SYMATTR Value 820
SYMBOL res 256 48 R0
SYMATTR InstName R3
SYMATTR Value 80K
SYMBOL res 352 48 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 528 48 R0
SYMATTR InstName R5
SYMATTR Value 5.1K
SYMBOL res 624 48 R0
SYMATTR InstName R6
SYMATTR Value 510
SYMBOL res -32 48 R0
SYMATTR InstName R1
SYMATTR Value 2.7K
SYMBOL njf 48 240 R0
WINDOW 3 54 60 Left 2
SYMATTR InstName J1
SYMATTR Value 2N5486
SYMBOL res 80 336 R0
WINDOW 0 35 59 Left 2
WINDOW 3 22 90 Left 2
SYMATTR InstName R8
SYMATTR Value 4.02K
SYMBOL res -32 336 R0
SYMATTR InstName R7
SYMATTR Value 4K
SYMBOL cap -48 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100µ
SYMBOL cap 160 368 R0
SYMATTR InstName C3
SYMATTR Value 4.7µ
SYMBOL cap 208 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100µ
SYMBOL npn 304 208 R0
SYMATTR InstName Q1
SYMATTR Value 2N5210
SYMBOL res 352 336 R0
SYMATTR InstName R10
SYMATTR Value 2K
SYMBOL cap 432 368 R0
SYMATTR InstName C5
SYMATTR Value 4.7µ
SYMBOL res 256 336 R0
SYMATTR InstName R9
SYMATTR Value 39K
SYMBOL npn 576 208 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 624 336 R0
SYMATTR InstName R12
SYMATTR Value 470
SYMBOL cap 720 368 R0
SYMATTR InstName C6
SYMATTR Value 4.7µ
SYMBOL cap 480 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100µ
SYMBOL res 528 336 R0
SYMATTR InstName R11
SYMATTR Value 4.7K
SYMBOL cap 784 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 100µ
SYMBOL voltage -144 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 .01 1000)
SYMATTR Value2 AC 1
SYMBOL res 832 272 R0
SYMATTR InstName R13
SYMATTR Value 1000
SYMBOL voltage -256 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12
TEXT 38 520 Left 2 !;tran .01
TEXT -232 520 Left 2 !.ac oct 1024 10 100000

--
JF

Hello John, and thank you for this info. Unfortunately I can'tremember waht
to do with a netlist for LTSpice. Could you possibly spare a word or two,
and clue me in? I've only done this once before, I think, and the memory o
what I did eludes me.

Thanks,

Dave



Just in case JF might take a while,
copy and paste the text into wordpad or similar program and save as
..txt into a file with an extention of .asc and you should be able
to open it with LTspice.

boB

boB wrote in message ...
On Sat, 14 Jan 2012 19:32:42 -0600, "Dave" wrote:


"John Fields" wrote in message
. ..
On Fri, 13 Jan 2012 11:00:18 -0600, "Dave" wrote:



Thoughts and suggestions are again welcome and sought.

Thanks,

Dave

---
Version 4
SHEET 1 932 680
WIRE -16 16 -256 16
WIRE 96 16 -16 16
WIRE 272 16 96 16
WIRE 368 16 272 16
WIRE 544 16 368 16
WIRE 640 16 544 16
WIRE -16 64 -16 16
WIRE 96 64 96 16
WIRE 272 64 272 16
WIRE 368 64 368 16
WIRE 544 64 544 16
WIRE 640 64 640 16
WIRE 96 192 96 144
WIRE 144 192 96 192
WIRE 272 192 272 144
WIRE 272 192 208 192
WIRE 368 192 368 144
WIRE 416 192 368 192
WIRE 544 192 544 144
WIRE 544 192 480 192
WIRE 640 192 640 144
WIRE 720 192 640 192
WIRE 848 192 784 192
WIRE 368 208 368 192
WIRE 640 208 640 192
WIRE 96 240 96 192
WIRE 272 256 272 192
WIRE 304 256 272 256
WIRE 544 256 544 192
WIRE 576 256 544 256
WIRE -112 288 -144 288
WIRE -16 288 -16 144
WIRE -16 288 -48 288
WIRE 848 288 848 192
WIRE -16 304 -16 288
WIRE 48 304 -16 304
WIRE 176 336 96 336
WIRE 368 336 368 304
WIRE 448 336 368 336
WIRE 640 336 640 304
WIRE 736 336 640 336
WIRE -16 352 -16 304
WIRE 96 352 96 336
WIRE 272 352 272 256
WIRE 368 352 368 336
WIRE 544 352 544 256
WIRE 640 352 640 336
WIRE -256 368 -256 16
WIRE -144 368 -144 288
WIRE 176 368 176 336
WIRE 448 368 448 336
WIRE 736 368 736 336
WIRE -256 480 -256 448
WIRE -144 480 -144 448
WIRE -144 480 -256 480
WIRE -16 480 -16 432
WIRE -16 480 -144 480
WIRE 96 480 96 432
WIRE 96 480 -16 480
WIRE 176 480 176 432
WIRE 176 480 96 480
WIRE 272 480 272 432
WIRE 272 480 176 480
WIRE 368 480 368 432
WIRE 368 480 272 480
WIRE 448 480 448 432
WIRE 448 480 368 480
WIRE 544 480 544 432
WIRE 544 480 448 480
WIRE 640 480 640 432
WIRE 640 480 544 480
WIRE 736 480 736 432
WIRE 736 480 640 480
WIRE 848 480 848 368
WIRE 848 480 736 480
WIRE -256 544 -256 480
FLAG -256 544 0
SYMBOL res 80 48 R0
SYMATTR InstName R2
SYMATTR Value 820
SYMBOL res 256 48 R0
SYMATTR InstName R3
SYMATTR Value 80K
SYMBOL res 352 48 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 528 48 R0
SYMATTR InstName R5
SYMATTR Value 5.1K
SYMBOL res 624 48 R0
SYMATTR InstName R6
SYMATTR Value 510
SYMBOL res -32 48 R0
SYMATTR InstName R1
SYMATTR Value 2.7K
SYMBOL njf 48 240 R0
WINDOW 3 54 60 Left 2
SYMATTR InstName J1
SYMATTR Value 2N5486
SYMBOL res 80 336 R0
WINDOW 0 35 59 Left 2
WINDOW 3 22 90 Left 2
SYMATTR InstName R8
SYMATTR Value 4.02K
SYMBOL res -32 336 R0
SYMATTR InstName R7
SYMATTR Value 4K
SYMBOL cap -48 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100µ
SYMBOL cap 160 368 R0
SYMATTR InstName C3
SYMATTR Value 4.7µ
SYMBOL cap 208 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100µ
SYMBOL npn 304 208 R0
SYMATTR InstName Q1
SYMATTR Value 2N5210
SYMBOL res 352 336 R0
SYMATTR InstName R10
SYMATTR Value 2K
SYMBOL cap 432 368 R0
SYMATTR InstName C5
SYMATTR Value 4.7µ
SYMBOL res 256 336 R0
SYMATTR InstName R9
SYMATTR Value 39K
SYMBOL npn 576 208 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 624 336 R0
SYMATTR InstName R12
SYMATTR Value 470
SYMBOL cap 720 368 R0
SYMATTR InstName C6
SYMATTR Value 4.7µ
SYMBOL cap 480 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100µ
SYMBOL res 528 336 R0
SYMATTR InstName R11
SYMATTR Value 4.7K
SYMBOL cap 784 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 100µ
SYMBOL voltage -144 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 .01 1000)
SYMATTR Value2 AC 1
SYMBOL res 832 272 R0
SYMATTR InstName R13
SYMATTR Value 1000
SYMBOL voltage -256 352 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12
TEXT 38 520 Left 2 !;tran .01
TEXT -232 520 Left 2 !.ac oct 1024 10 100000

--
JF

Hello John, and thank you for this info. Unfortunately I can'tremember
waht
to do with a netlist for LTSpice. Could you possibly spare a word or two,
and clue me in? I've only done this once before, I think, and the memory
o
what I did eludes me.

Thanks,

Dave



Just in case JF might take a while,
copy and paste the text into wordpad or similar program and save as
.txt into a file with an extention of .asc and you should be able
to open it with LTspice.

boB






Well *thank you* Bob. I do appreciate the help...

Dave

"Dave" wrote:

Well *thank you* Bob. I do appreciate the help...

Dave

Dave, the first stage has an attenuation of 21dB. I'd run it in Transient
Analysis first and get the bias and load conditions set properly before
messing with Frequency Analysis.

Mike

"Mike" wrote in message
...
"Dave" wrote:

Well *thank you* Bob. I do appreciate the help...

Dave

Dave, the first stage has an attenuation of 21dB. I'd run it in Transient
Analysis first and get the bias and load conditions set properly before
messing with Frequency Analysis.

Mike

Hey Mike,

Yes, I was working with it on the workbench today, and could hardly believe
it's lack of performance. Definetely needs more work. Wish I had a copy of
Electronics Workbench. Thanks for the encouragement.

Dave

"Dave" wrote in message
.. .

"Mike" wrote in message
...
"Dave" wrote:

Well *thank you* Bob. I do appreciate the help...

Dave

Dave, the first stage has an attenuation of 21dB. I'd run it in Transient
Analysis first and get the bias and load conditions set properly before
messing with Frequency Analysis.

Mike

Hey Mike,

Yes, I was working with it on the workbench today, and could hardly
believe it's lack of performance. Definetely needs more work. Wish I had
a copy of Electronics Workbench. Thanks for the encouragement.

Dave



Neglected to mention I got stage one running okay *I think* by replacing R7
with a 1.5K resistor. Doesn't do a damn thing for the rest of the circuit,
but I'm working on that...

Thanks.

"Dave" wrote:


Neglected to mention I got stage one running okay *I think* by
replacing R7 with a 1.5K resistor. Doesn't do a damn thing for the
rest of the circuit, but I'm working on that...

Thanks.

I don't have a copy of the circuit any more, but I wonder if there's a
reason you want a FET as the first stage? It seemed there were fairly low
value resistors in the input bias network. These would swamp the high input
impedance of the FET gate.

So a good bipolar at the input might be a better match and have lower noise
at that impedance level.

Mike

"Mike" wrote in message
...
"Dave" wrote:


Neglected to mention I got stage one running okay *I think* by
replacing R7 with a 1.5K resistor. Doesn't do a damn thing for the
rest of the circuit, but I'm working on that...

Thanks.

I don't have a copy of the circuit any more, but I wonder if there's a
reason you want a FET as the first stage? It seemed there were fairly low
value resistors in the input bias network. These would swamp the high
input
impedance of the FET gate.

So a good bipolar at the input might be a better match and have lower
noise
at that impedance level.

Mike

Hey Mike, sorry it took me so long to get back to you. I was wanting to use
a JFET at the input due to the high impedance value of such a device, since
I'm hooking it directly to the microphone of the intercom. And I was
originally using the 1.5K and 4K resistors so I could use the 4.02K resistor
to drive the source. I am no longer attempting to bias the device so close
to pinch-off however, (which is what the 4.02K resistor was about) so I
supppose I could change these at his point. I must admit I am not certain
what you mean by the potential for these low-value resistors swamping the
high impedance of the JFET. As I mentioned earlier, I am NOT an EE, and am
learning this as I go along. Any info you could give me on this subject,
or as to what to look up in my textbooks, would be most appreciated.
Attached is a copy of the current version of the schematic I am working
with. I am wanting to use a 25K pot to control the output, but am not
certain as to where to put it. (Was originally thinking of putting it
between the drain of J1 and capacitor C6, but am not sure if that is
actually the best place for it. Also, the 5 Ohm resistors (R4 and R1) are
something I simply plugged in, and are obviously not written in stone.
LTSpice says this circuit ought to work like gangbusters though. Maybe too
well...

Thanks for the feedback.

On Thu, 19 Jan 2012 05:41:20 -0600, "Dave" wrote:


Hey Mike, sorry it took me so long to get back to you. I was wanting to use
a JFET at the input due to the high impedance value of such a device, since
I'm hooking it directly to the microphone of the intercom. And I was
originally using the 1.5K and 4K resistors so I could use the 4.02K resistor
to drive the source. I am no longer attempting to bias the device so close
to pinch-off however, (which is what the 4.02K resistor was about) so I
supppose I could change these at his point. I must admit I am not certain
what you mean by the potential for these low-value resistors swamping the
high impedance of the JFET. As I mentioned earlier, I am NOT an EE, and am
learning this as I go along. Any info you could give me on this subject,
or as to what to look up in my textbooks, would be most appreciated.
Attached is a copy of the current version of the schematic I am working
with. I am wanting to use a 25K pot to control the output, but am not
certain as to where to put it. (Was originally thinking of putting it
between the drain of J1 and capacitor C6, but am not sure if that is
actually the best place for it. Also, the 5 Ohm resistors (R4 and R1) are
something I simply plugged in, and are obviously not written in stone.
LTSpice says this circuit ought to work like gangbusters though. Maybe too
well...

Thanks for the feedback.


The input impedance of the amplifier includes the effect of _all_
components connected to the input, not just the input impedance of the
Jfet. Since both ground and +12V are effectively at AC ground, the
two input resistors are in parallel to ground, as far as the input
signal is concerned, so your input impedance is 1.5K in parallel with
4K, or about 900 ohms.

Incidently, we usually use "Q" as the reference prefix for all
transistor-like devices. "J" is usually used for a connector (jack).
--
Peter Bennett, VE7CEI
peterbb (at) telus.net
GPS and NMEA info: http://vancouver-webpages.com/peter
Vancouver Power Squadron: http://vancouver.powersquadron.ca

"Peter Bennett" wrote in message
news.com...
On Thu, 19 Jan 2012 05:41:20 -0600, "Dave" wrote:


Hey Mike, sorry it took me so long to get back to you. I was wanting to
use
a JFET at the input due to the high impedance value of such a device,
since
I'm hooking it directly to the microphone of the intercom. And I was
originally using the 1.5K and 4K resistors so I could use the 4.02K
resistor
to drive the source. I am no longer attempting to bias the device so
close
to pinch-off however, (which is what the 4.02K resistor was about) so I
supppose I could change these at his point. I must admit I am not certain
what you mean by the potential for these low-value resistors swamping the
high impedance of the JFET. As I mentioned earlier, I am NOT an EE, and
am
learning this as I go along. Any info you could give me on this subject,
or as to what to look up in my textbooks, would be most appreciated.
Attached is a copy of the current version of the schematic I am working
with. I am wanting to use a 25K pot to control the output, but am not
certain as to where to put it. (Was originally thinking of putting it
between the drain of J1 and capacitor C6, but am not sure if that is
actually the best place for it. Also, the 5 Ohm resistors (R4 and R1) are
something I simply plugged in, and are obviously not written in stone.
LTSpice says this circuit ought to work like gangbusters though. Maybe
too
well...

Thanks for the feedback.


The input impedance of the amplifier includes the effect of _all_
components connected to the input, not just the input impedance of the
Jfet. Since both ground and +12V are effectively at AC ground, the
two input resistors are in parallel to ground, as far as the input
signal is concerned, so your input impedance is 1.5K in parallel with
4K, or about 900 ohms.

Incidently, we usually use "Q" as the reference prefix for all
transistor-like devices. "J" is usually used for a connector (jack).
--
Peter Bennett, VE7CEI
peterbb (at) telus.net
GPS and NMEA info: http://vancouver-webpages.com/peter
Vancouver Power Squadron: http://vancouver.powersquadron.ca

Thank you, Peter, for this feedback and info. I must admit I am still
struggling to understand input and output impedances (obviously) but your
post makes it pretty clear. Thanks.

And yes, I know that transistors and transistor-like devices are usually
referred to as Qx and not Jx, but that was put there by the version os Spice
I am using for circuit simulation, and I didn't argue about it. Figured
maybe this was something else I just didnt know...

'preciate it.

Dave