Copy all of the files into a single folder, navigate to and open the
folder with LTspice, and run the files.

There are 4 and 8 bit versions of the ADC included.


--
JF

On Tue, 04 Oct 2011 07:29:32 -0500, John Fields
wrote:


Copy all of the files into a single folder, navigate to and open the
folder with LTspice, and run the files.

There are 4 and 8 bit versions of the ADC included.

---
Improved some stuff...

--
JF

On Tue, 04 Oct 2011 07:29:32 -0500, John Fields
wrote:


Copy all of the files into a single folder, navigate to and open the
folder with LTspice, and run the files.

There are 4 and 8 bit versions of the ADC included.




Now that's pretty cool !

Haven't stared at it long and I don't think I know
all I understand about it, but nice waveforms !!

boB

On 6 Oct 2011 16:33:01 -0500, boB wrote:

On Tue, 04 Oct 2011 07:29:32 -0500, John Fields
wrote:


Copy all of the files into a single folder, navigate to and open the
folder with LTspice, and run the files.

There are 4 and 8 bit versions of the ADC included.




Now that's pretty cool !

Haven't stared at it long and I don't think I know
all I understand about it, but nice waveforms !!

boB
---
Thanks! :-)

Here's how the 4 bit one works:

U1 is a 4 bit up/down binary counter, U2 is a comparator, U3 is a
fairly fast rail-to-rail input and output opamp, the resistors
connected to the outputs of the counter form an R-2R ladder, and the
circuit is a tracking analog-to-digital converter with its internal
DAC being U1 and the R-2R ladder.

R1-C1 is a differentiator which asynchronously broadside loads zeroes
into U1, during power-up, causing the output of the R-2R ladder (VDAC)
to go to zero.

When that happens the output of U2 (D/U) will go low, unconditionally,
(notice the small offset above 0V generated by V4 in order to
compensate for the non-zero Vol of the logic) and, since S\H is low,
will cause the counter to start counting up from zero.

That'll cause VDAC to increase with each clock pulse until VDACVin.

When that happens, D\U changes sign and forces the counter to count
down until VDACVin.

Then the cycle repeats, forever, or until S/H goes high, at which time
Vout will be equal to Vin +/- 1 count, as long as S/H is held high.

--
JF