Improvements help please
 

See attached PDF.
Basically, current thru the DUT is set by adjusting a series resistor
to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple in
the 2800V supply shows across the DUT (10Meg resistor used for analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a constant
current instead.
Useful comments please?

Improvements help please
 

On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series resistor
to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple in
the 2800V supply shows across the DUT (10Meg resistor used for analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a constant
current instead.
Useful comments please?

The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.

It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John

Improvements help please
 

John Larkin wrote:
On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series resistor
to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple in
the 2800V supply shows across the DUT (10Meg resistor used for analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a constant
current instead.
Useful comments please?

The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.

It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John



I tried removing the 4.7uF cap as it seemed "obvious", and not only
did the ripple current get worse, there were more power line harmonics.
I tried a 4700pF cap across one of the 100Meg resistors ("bottom"
one), to no avail so i quit that nonsense.
I tried a 4700pF cap across the supply and that reduced the ripple
some - not a lot. Large value 3KV caps are not exactly common, small or
inexpensive. Looks i would need a cap in the region of 1uF..

I came up with a better way of driving the FETs; all i need is a
500KC oscillator with RMS output near input voltage - say oscillates
from 1V to 5V in.
See attached PDF.

Improvements help please
 

Robert Baer wrote:
John Larkin wrote:
On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series
resistor to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple
in the 2800V supply shows across the DUT (10Meg resistor used for
analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a
constant current instead.
Useful comments please?

The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.
It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John



I tried removing the 4.7uF cap as it seemed "obvious", and not only
did the ripple current get worse, there were more power line harmonics.
I tried a 4700pF cap across one of the 100Meg resistors ("bottom"
one), to no avail so i quit that nonsense.
I tried a 4700pF cap across the supply and that reduced the ripple
some - not a lot. Large value 3KV caps are not exactly common, small or
inexpensive. Looks i would need a cap in the region of 1uF..

I came up with a better way of driving the FETs; all i need is a 500KC
oscillator with RMS output near input voltage - say oscillates from 1V
to 5V in.
See attached PDF.

OOPS! See a big goofus (me); the top 2 drivers are shorted - should
go from the source too the gate..
Perhaps with a better gate drive, removing C2 would be a benefit.

Improvements help please
 

On Sat, 23 Oct 2010 20:15:53 -0700, Robert Baer
wrote:

Robert Baer wrote:
John Larkin wrote:
On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series
resistor to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple
in the 2800V supply shows across the DUT (10Meg resistor used for
analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a
constant current instead.
Useful comments please?

The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.
It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John



I tried removing the 4.7uF cap as it seemed "obvious", and not only
did the ripple current get worse, there were more power line harmonics.
I tried a 4700pF cap across one of the 100Meg resistors ("bottom"
one), to no avail so i quit that nonsense.
I tried a 4700pF cap across the supply and that reduced the ripple
some - not a lot. Large value 3KV caps are not exactly common, small or
inexpensive. Looks i would need a cap in the region of 1uF..

I came up with a better way of driving the FETs; all i need is a 500KC
oscillator with RMS output near input voltage - say oscillates from 1V
to 5V in.
See attached PDF.

OOPS! See a big goofus (me); the top 2 drivers are shorted - should
go from the source too the gate..
Perhaps with a better gate drive, removing C2 would be a benefit.

This circuit is sufficiently complex, the solution space is so huge,
that you are unlikely to stumble onto a good design by fiddling.

John

Improvements help please
 

John Larkin wrote:
On Sat, 23 Oct 2010 20:15:53 -0700, Robert Baer
wrote:

Robert Baer wrote:
John Larkin wrote:
On Sat, 23 Oct 2010 00:58:17 -0700, Robert Baer
wrote:

See attached PDF.
Basically, current thru the DUT is set by adjusting a series
resistor to get one volt.
The average reading of voltage is fairly decent, but the actual
voltage across the DUT is not so nice (to be polite); the 200V ripple
in the 2800V supply shows across the DUT (10Meg resistor used for
analysis).
Believe it or not, using the capacitor values shown for C1 and C2
appear to be optimum for that average reading..
It would be nice to get the opamp + FET chain to work for a
constant current instead.
Useful comments please?
The current regulator loop dynamics changes radically as you change
the shunt resistors. With 50K and 4.7 uF, the corner frequency is
under 1 Hz, so any ripple in the DUT current is hugely attenuated
before it gets to the error amp.
It would be better to use a single shunt and adjust the voltage
reference, so you can better tune loop dynamics and reduce ripple.
You'll need a pretty fast loop (and maybe a little feed-forward hum
nulling) to supress that power supply ripple.

Can't you filter the supply better, too?

Some caps across your 100M resistors might help.

Spicing is in order!


John



I tried removing the 4.7uF cap as it seemed "obvious", and not only
did the ripple current get worse, there were more power line harmonics.
I tried a 4700pF cap across one of the 100Meg resistors ("bottom"
one), to no avail so i quit that nonsense.
I tried a 4700pF cap across the supply and that reduced the ripple
some - not a lot. Large value 3KV caps are not exactly common, small or
inexpensive. Looks i would need a cap in the region of 1uF..

I came up with a better way of driving the FETs; all i need is a 500KC
oscillator with RMS output near input voltage - say oscillates from 1V
to 5V in.
See attached PDF.

OOPS! See a big goofus (me); the top 2 drivers are shorted - should
go from the source too the gate..
Perhaps with a better gate drive, removing C2 would be a benefit.

This circuit is sufficiently complex, the solution space is so huge,
that you are unlikely to stumble onto a good design by fiddling.

John

OK, here is a step towards SPICE modeling the beast..without current
sense / feedback; just a fixed but adjustable drive level.
Spice takes forever; i do not have days to wait; it steps in the tens
of nanoseconds region and i want to see the voltage on the top FET drain
to look at the ripple there (10mSec time frame).
Without the FETs, it converges in less than a second.
What can i do to make it faster?

Version 4
SHEET 1 1140 680
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SYMATTR Value STW11NM80
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SYMATTR Value STW11NM80
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SYMATTR SpiceLine pwr=10
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SYMATTR Value 100Meg
SYMBOL res 464 -608 R0
SYMATTR InstName R13
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TEXT -112 256 Left 0 !K1 L1 L2 0.998
TEXT -400 328 Left 0 ;Output level set
TEXT -120 232 Left 0 ;Murata 78601/2C
TEXT -120 -56 Left 0 ;Murata 78601/2C
TEXT -104 -32 Left 0 !K2 L3 L4 0.998
TEXT -136 -328 Left 0 ;Murata 78601/2C
TEXT -120 -304 Left 0 !K3 L5 L6 0.998
TEXT -618 -312 Left 0 !.tran 0 20ms 0

Improvements help please (Speedups?)
 

I dumped excess stuff for the sort term and set a time as short as
possible but still see step response to settling.
The 555 oscillator is "steady state" around 0.18mSec, so i start my
pulse at 0.2mSec; the output then is stable around 0.45mSec so my pulse
reverts at 0.5mSec; the result settling around 0.9mSec.
It still takes a while to run - simulator runs about 20uSec/second to
generate data.
I would like this to run perhaps 10 times faster so that i can do a
full schematic over a 100mSec or longer period of time - without having
to wait days.
Help?
What i have now:

Version 4
SHEET 1 1140 680
WIRE -240 -144 -512 -144
WIRE -928 -80 -1072 -80
WIRE -640 -80 -928 -80
WIRE -352 -80 -640 -80
WIRE -352 -32 -352 -80
WIRE -1072 -16 -1072 -80
WIRE -912 -16 -1008 -16
WIRE -640 -16 -640 -80
WIRE -640 -16 -688 -16
WIRE -592 -16 -640 -16
WIRE -512 16 -512 -144
WIRE -416 16 -512 16
WIRE 176 32 -16 32
WIRE -912 48 -976 48
WIRE -624 48 -688 48
WIRE -128 48 -144 48
WIRE 176 48 176 32
WIRE 176 48 144 48
WIRE 208 48 176 48
WIRE 336 48 304 48
WIRE -1008 64 -1008 -16
WIRE -1008 64 -1072 64
WIRE -208 64 -208 48
WIRE -208 64 -352 64
WIRE -128 64 -128 48
WIRE -80 64 -128 64
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WIRE 400 64 336 64
WIRE -1072 80 -1072 64
WIRE 400 80 400 64
WIRE -624 96 -624 48
WIRE -592 96 -592 64
WIRE -592 96 -624 96
WIRE -352 96 -352 64
WIRE 304 96 304 48
WIRE 304 96 176 96
WIRE -912 112 -944 112
WIRE -640 112 -688 112
WIRE -592 112 -592 96
WIRE 176 112 176 96
WIRE 176 112 144 112
WIRE 256 112 208 112
WIRE -512 128 -512 16
WIRE -432 128 -512 128
WIRE -208 128 -208 64
WIRE -128 128 -128 64
WIRE 256 128 256 112
WIRE 304 128 256 128
WIRE -432 144 -432 128
WIRE -240 144 -240 -144
WIRE -240 144 -288 144
WIRE 400 144 336 144
WIRE -1008 176 -1008 64
WIRE -1008 176 -1040 176
WIRE -928 176 -928 -80
WIRE -912 176 -928 176
WIRE 176 176 144 176
WIRE 208 176 176 176
WIRE 304 176 304 128
WIRE 336 176 336 144
WIRE 336 176 304 176
WIRE 592 176 336 176
WIRE -512 192 -512 128
WIRE -80 192 -80 144
WIRE -16 192 -16 144
WIRE 176 192 176 176
WIRE 176 192 -16 192
WIRE -640 208 -640 112
WIRE -592 208 -592 192
WIRE -592 208 -640 208
WIRE 592 208 592 176
WIRE -352 240 -352 192
WIRE -432 256 -432 208
WIRE -1040 272 -1040 176
WIRE -976 272 -976 48
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WIRE -592 272 -976 272
WIRE -944 304 -944 112
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WIRE -512 304 -944 304
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FLAG 592 208 0
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WINDOW 3 -51 96 Left 0
SYMATTR Value 2N2222
SYMATTR InstName Q1
SYMBOL res -112 112 R90
WINDOW 3 32 56 VTop 0
WINDOW 0 92 62 VBottom 0
SYMATTR Value 1K
SYMATTR InstName R1
SYMBOL voltage -1072 -32 R0
WINDOW 0 13 4 Left 0
WINDOW 3 9 -24 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15V
SYMBOL cap -208 64 R270
WINDOW 3 -6 37 VBottom 0
WINDOW 0 30 2 VTop 0
SYMATTR Value 4.7µ
SYMATTR InstName C1
SYMBOL Misc\\NE555 -800 80 R0
SYMATTR InstName U1
SYMBOL res -608 -32 R0
SYMATTR InstName R8
SYMATTR Value 910
SYMBOL res -608 96 R0
WINDOW 0 38 49 Left 0
WINDOW 3 32 90 Left 0
SYMATTR InstName R9
SYMATTR Value 910
SYMBOL cap -1040 288 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 -12 37 VBottom 0
SYMATTR InstName C6
SYMATTR Value 0.001µ
SYMBOL res -528 176 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL diode -448 144 R0
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage -432 240 R0
WINDOW 0 30 17 Left 0
WINDOW 3 46 57 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(8 2 200u 100n 100n 300u)
SYMBOL ind2 -96 48 R0
WINDOW 3 -42 113 Left 0
SYMATTR Value 500µ
SYMATTR InstName L1
SYMBOL ind2 -32 48 R0
WINDOW 3 35 116 Left 0
SYMATTR Value 500µ
SYMATTR InstName L2
SYMBOL pnp -288 192 R180
WINDOW 0 42 52 Left 0
WINDOW 3 -29 -9 Left 0
SYMATTR InstName Q2
SYMATTR Value 2N2907
SYMBOL res 320 48 R0
WINDOW 3 25 84 Left 0
SYMATTR Value 10K
SYMATTR InstName R3
SYMBOL diode 128 48 R0
WINDOW 0 -34 30 Left 0
WINDOW 3 -69 2 Left 0
SYMATTR InstName D10
SYMATTR Value 1N4148
SYMBOL diode 160 176 R180
WINDOW 0 37 32 Left 0
WINDOW 3 22 4 Left 0
SYMATTR InstName D11
SYMATTR Value 1N4148
SYMBOL diode 224 112 R180
WINDOW 0 -34 32 Left 0
WINDOW 3 -68 60 Left 0
SYMATTR InstName D12
SYMATTR Value 1N4148
SYMBOL diode 192 112 R0
WINDOW 0 38 30 Left 0
WINDOW 3 23 63 Left 0
SYMATTR InstName D13
SYMATTR Value 1N4148
SYMBOL cap 384 80 R0
WINDOW 0 -12 -33 Left 0
WINDOW 3 -32 83 Left 0
SYMATTR InstName C4
SYMATTR Value 0.012µ
TEXT -112 256 Left 0 !K1 L1 L2 0.998
TEXT -400 328 Left 0 ;Output level set
TEXT -120 232 Left 0 ;Murata 78601/2C
TEXT -616 -312 Left 0 !.tran 0 1ms 0

Improvements help please (Speedups?)
 

Fundamental Thompson Rule... learned the hard way:

"If Spice struggles to find convergence you have a bad design" :-)

On Mon, 25 Oct 2010 02:21:05 -0700, Robert Baer
wrote:

I dumped excess stuff for the sort term and set a time as short as
possible but still see step response to settling.
The 555 oscillator is "steady state" around 0.18mSec, so i start my
pulse at 0.2mSec; the output then is stable around 0.45mSec so my pulse
reverts at 0.5mSec; the result settling around 0.9mSec.
It still takes a while to run - simulator runs about 20uSec/second to
generate data.
I would like this to run perhaps 10 times faster so that i can do a
full schematic over a 100mSec or longer period of time - without having
to wait days.
Help?
What i have now:

Version 4
SHEET 1 1140 680
WIRE -240 -144 -512 -144
WIRE -928 -80 -1072 -80
[snip]
TEXT -112 256 Left 0 !K1 L1 L2 0.998
TEXT -400 328 Left 0 ;Output level set
TEXT -120 232 Left 0 ;Murata 78601/2C
TEXT -616 -312 Left 0 !.tran 0 1ms 0

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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I can see November from my house :-)