Er, well.. surely an LFSR will be flat, not Gaussian, no?
Fortunately, there is an app\\\ transform for that:
http://www.design.caltech.edu/erik/Misc/Gaussian.html
shouldn't be too bad to implement on FPGA. Log can be very crudely
obtained as the highest active ('1') bit position, and can be improved
iteratively (by repeated squarings and bit-shifts, or Taylor series
polynomial approximation methods).
Obviously, to shoot it out of a DAC, the bounds must be strictly limited,
so part of your spec will be how many sigma of Gaussian it's good for
(usually 3 or so?).
Which, in turn, implies that the argument of the log can't be near zero
(which is what produces the peaky outliers), and certainly can't be zero
exactly (which would be undefined), so perhaps the LFSR's inherent bias
could be tuned to match the dynamic range of the desired output? Nah,
probably not, not for any reasonable sequence length. So you'll have to
do something ugly (and hopefully not badly behaved), like RND * scale +
offset.
There are also methods for that -- ensuring that an output of truncated,
arbitrary range is calculated correctly from an even distribution in some
other range.
The geometric form is interesting, too; a random time delay could trigger
a S&H of complementary (90 degree phase shifted) sine waves, and the other
random number could feed a suitable arrangement of matched diode junctions
or OTAs which computes the sqrt(ln(x)) function, and simultaneously
controls the gain on the S&H buffers.
The "random" time delay has a strictly bounded range, so it could be
triggered on a fixed clock, 'computed', then 'registered' with a second
S&H on the following clock pulse, to give regularly sampled outputs (same
as you'd use extra D-flops to neaten up the transitions in a digital logic
circuit). Who even needs a DAC?
Or you could randomly sample a sin/cos table and vary the VREF into an
MDAC, or...
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website:
http://seventransistorlabs.com
"John Larkin" wrote in message
...
On Wed, 01 Apr 2015 11:00:25 -0700, Jim Thompson
wrote:
For a simulation situation I need a random number generator with a
twist...
What I need to simulate is a "random" selection of one-of-16 outputs.
Clock "speed" is 12.5kHz ;-)
Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.
Thanks in advance.
...Jim Thompson
Only vaguely on-topic, here is a noise generator experiment. The mess
on the left makes 1-bit digital noise clocked at 1 MHz, like a linear
shift register, just easier to draw. The issue at hand is what kind of
lowpass filter to use to get approximately Gaussian noise.
The 200 KHz filter is right out of AoE3 p 559. It looks fine in the
audio frequency domain, but it's nothing like Gaussian.
The 3-pole filter is a lot nicer.
We're actually going to use a LFSR in an FPGA and do the serious
filtering digitally, and drive a DAC with a little analog filtering
afterwards.
Version 4
SHEET 1 1316 680
WIRE 912 -64 848 -64
WIRE 1056 -64 912 -64
WIRE 1200 -64 1136 -64
WIRE 1248 -64 1200 -64
WIRE 1312 -64 1248 -64
WIRE 1200 -16 1200 -64
WIRE 368 64 208 64
WIRE 480 64 368 64
WIRE 208 96 208 64
WIRE 1200 96 1200 48
WIRE 720 112 656 112
WIRE 752 112 720 112
WIRE 432 128 400 128
WIRE 480 128 432 128
WIRE 208 208 208 176
WIRE 848 208 848 -64
WIRE 912 208 848 208
WIRE 1056 208 992 208
WIRE 1200 208 1136 208
WIRE 1248 208 1200 208
WIRE 1312 208 1248 208
WIRE 848 240 848 208
WIRE 400 256 400 128
WIRE 1200 256 1200 208
WIRE 400 368 400 336
WIRE 848 368 848 320
WIRE 1200 368 1200 320
FLAG 208 208 0
FLAG 368 64 NOISE
FLAG 400 368 0
FLAG 720 112 SH
FLAG 848 368 0
FLAG 912 -64 COMP
FLAG 1200 368 0
FLAG 1248 208 LPF2
FLAG 432 128 CLK
FLAG 1200 96 0
FLAG 1248 -64 LPF1
SYMBOL bv 208 80 R0
WINDOW 0 -63 105 Left 2
WINDOW 3 -131 174 Left 2
SYMATTR InstName B1
SYMATTR Value V=random(1.83e7*time) - 0.5
SYMBOL SpecialFunctions\\sample 560 96 R0
SYMATTR InstName A1
SYMBOL voltage 400 240 R0
WINDOW 0 -85 76 Left 2
WINDOW 3 -323 114 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 500n 1u)
SYMBOL bv 848 224 R0
WINDOW 0 -120 42 Left 2
WINDOW 3 -187 87 Left 2
SYMATTR InstName B2
SYMATTR Value V=sgn(v(sh))
SYMBOL res 1152 192 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 1184 256 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C1
SYMATTR Value 5n
SYMBOL res 1152 -80 R90
WINDOW 0 69 58 VBottom 2
WINDOW 3 75 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5K
SYMBOL cap 1184 -16 R0
WINDOW 0 51 15 Left 2
WINDOW 3 50 51 Left 2
SYMATTR InstName C2
SYMATTR Value 150p
SYMBOL ind 896 224 R270
WINDOW 0 -33 54 VTop 2
WINDOW 3 -39 51 VBottom 2
SYMATTR InstName L1
SYMATTR Value 17m
TEXT 552 -48 Left 2 !.tran 25m
TEXT 216 -72 Left 2 ;Noise Generator Test
TEXT 208 -32 Left 2 ;J Larkin April 28, 2015
TEXT 432 240 Left 2 ;1 MHz CLOCK
TEXT 640 352 Left 2 ;COMPARATOR
TEXT 1056 48 Left 2 ;200 KHz
TEXT 1056 312 Left 2 ;20 KHz
TEXT 864 56 Left 2 ;DIGITAL
TEXT 864 88 Left 2 ;NOISE
--
John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com