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rickman rickman is offline
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Default "Random" Circuit Needed.

On 4/26/2015 6:29 PM, John Fields wrote:
On Sun, 26 Apr 2015 09:32:00 -0400, rickman

On 4/25/2015 5:23 PM, John Fields wrote:
On Sat, 25 Apr 2015 15:49:06 -0400, rickman

On 4/23/2015 8:06 PM, John Fields wrote:
On Wed, 22 Apr 2015 13:35:38 -0400, rickman

On 4/18/2015 6:46 PM, John Fields wrote:
On Fri, 17 Apr 2015 14:33:40 -0400, rickman

On 4/17/2015 9:11 AM, John Fields wrote:
On Fri, 17 Apr 2015 00:35:00 -0400, rickman

On 4/16/2015 11:25 PM, John Fields wrote:
On Thu, 16 Apr 2015 20:07:46 -0400, rickman

On 4/16/2015 4:46 PM, John Fields wrote:

If you need the extra state, then even for huge counters the
practicality fades into insignificance.

John Fields

I'm not sure what that means. Practicality is *always* an issue that
needs consideration. The primary point of LFSRs is that they can be
built to run quickly and take of little space because of the minimal
logic requirements. If you throw that away you can start looking at a
much larger field of contenders.

What it means is that arranging the feedback to convert a maximal
length (2^n)-1 LFSR into a PRSG with a count length of 2^n is
trivial compared with other methods.

Can you post a contradictory example culled from the "larger field
of contenders" ?

I don't see where you have provided any examples to contradict.

I already posted a link to an 8 bit PRSG with 256 output states.

Did you miss it?


Well, then, for your perusal, here ya go:

This is hardly a "huge" counter...

Indeed, but the point made was to illustrate that NORing the outputs
of all of the stages preceding the rightmost and using that feedback
to force the PRSG into and out of the lockup state would cause it to
visit all of the 2^n possible states for that length of PRSG.

Uh, I had already indicated that this was possible and posted a link to
Peter Alfkie's app note about this for small LFSRs. So you are
restating my point.

As I recall, the schematic your link pointed to was a little
confusing - to me, anyway - so I decided to post something better
organized in order to illustrate the concept more clearly, not to
mention a working simulation. Which, BTW, neither you nor Alfkie

In any case, just for your information, that circuit's been around
since at least the late '60s, when I first came across it being used
as a bias-free scrambler.

Faulting the example because the counter isn't huge is disingenuous
since, if the lockup state is needed as part of the pattern, all
that's really needed to scale up to any PRSG length is a bunch of
diodes, a pullup resistor to Vcc, and an inverter on the outputs of
the diodes.

A bunch of diodes? I guess so, but the speed issue still remains.

How so?

if the diodes are all commoned on one end and followed by an
inverter, then the worst case delay will be one gate plus one diode,
which should be less than the delay through a stage of shift and
then back to the input through an EXOR.

The speed of your breadboard circuit is not really relevant. The speed
of a VLSI ASIC or an FPGA is what 99.999% of people will care about.
There is a reason why DTL is no longer used. Besides, the circuit slows
down with every diode added.

If you go back to the beginning, you'll see that my offering was in
reference to Jim's request for a circuit which was to be simulated
in 74XX, so that's what he got.

I think you're wrong about the circuit slowing down since all the
shifters are being parallel clocked, making the delays per stage
equal except for skew.

Simulate it for yourself, it's easy enough to do. all you have to do
is edit the sim I posted by replacing the Ors with diodes and a
pullup, and run it.

I'm not following you. The registers don't dominate the delay, the
logic does. All the logic feeds one FF. The more inputs to the logic
the slower it gets.

The entire point of an LFSR is that the logic is small and simple with a
very short prop delay allowing fast speeds.

That's a rather myopic viewpoint since the main use of an LFSR, I
believe, is to generate a pseudo-random sequence regardless of the
rate at which it's doing so.

Really? There are many ways of generating PRS. There are trade-offs
with each one. If you don't need the speed or small size an LFSR has
disadvantages compared to many others.


Oring all the outputs of a 64 or 128 bit register is not so fast
or simple even if done using state of the techniques such as
diode logic. lol

"State of the techniques"???

LOL indeed, since you don't even know how to talk about what you
don't know enough to talk about and, instead, offer up snarkiness as
a substitute for smart.

Lol. Yes, a typo makes for snarkiness. How about *state of the art*
techniques..? Yes, I was being sarcastic to illustrate the silliness of
mentioning DTL in a discussion of speed in LFSRs.

Are we done?


There's still the issue of why you think delays are additive through
AND ed diodes, and why you think it's silly to use diode steering
when it's appropriate.

What is the cause of the delay in the circuit you describe? The real
issue is that the diode based circuit is impractical because no one
needs such a circuit stand alone using discrete parts. People use a
circuit like this in a design such as an FPGA or an ASIC where the
delays are in gates which are cumulative.

I'm pretty done with this conversation. It's not shedding any light at
this point. We are just rehashing the same stuff.