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Jasen Betts[_2_] Jasen Betts[_2_] is offline
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Default "Random" Circuit Needed.

On 2015-04-03, rickman wrote:
On 4/2/2015 7:52 PM, John Fields wrote:
On 2 Apr 2015 10:42:50 GMT, Jasen Betts wrote:

On 2015-04-01, Jim Thompson wrote:
On Thu, 02 Apr 2015 07:26:29 +1000, "David Eather"

On Thu, 02 Apr 2015 05:14:13 +1000, Jim Thompson

On Wed, 01 Apr 2015 15:07:54 -0400, Phil Hobbs

On 04/01/2015 02:00 PM, Jim Thompson wrote:
For a simulation situation I need a random number generator with a

What I need to simulate is a "random" selection of one-of-16 outputs.

Clock "speed" is 12.5kHz ;-)

Built of 74HCxx parts is preferred... I have a full ensemble of those
device in my PSpice library.

Thanks in advance.

...Jim Thompson

How random? You could use a 16-bit PRBS made from two HC299 and an
HC86. Feed back Q14 XOR Q13, and tap out four stages to a HC154 demux.
If you need better randomness, use four PRBSes of different length.


Phil Hobbs

I just need semi-random enough to test a fast AGC.

...Jim Thompson

there is a bias with the 8-bit just use the last 4 bit idea. With 255
'clocks' all states but 0000 will occur 16 times while 0000 will only
appear 15 - the cycle then repeats. The lack of the extra 0000 may cause
the bias point to continually drift high.

I was wondering about that myself... I'll see if there's a cure.

r=(75*r+74)%65537 visits 0-65535 with no gaps.

not that i'd want to build it using 74LS logic.

But, if you had to, what would it look like, schematic-wise?

it'd look A bit like a LFSR except with serial adders instead of XORS
and a bit tacked on to do the %65537

Given that task I'd take it as a hint to learn "FPGA"

Not so bad. 75 = 64 + 8 + 2 + 1. Include the constant 74 addition that
would be four adders. I assume the modulo value is a typo and should be
65536 which comes free. I don't recall any 8 bit adder chips, so using
4 bit ones that would need chips 7 since when adding 64 * r, the lower 4
bits are always zero.

no, 65537 is correct.

mod 65537 isn't too hard, it'd need a second shift register to subtract the overflow
from the low 16 bits and subsequently add one if that substraction overflows.

this doesn't visit all 65537 states either: 65536 loops back on itself.
but it's not a desirable state.

I did this in Z80 assembler back in the 80s it took, 15 or so op codes
and used all of one register bank (7x 8bit), and I think about 50 clock
cycles, so that'd manage 12.5Khz.

umop apisdn